From: Nicolai Hähnle <nicolai.haeh...@amd.com>
This is more expressive and simplifies a subsequent change.
v2:
- fix one more call-site after rebase
---
src/gallium/drivers/freedreno/a2xx/fd2_gmem.c | 12 ++++++------
src/gallium/drivers/freedreno/a3xx/fd3_gmem.c | 4 ++--
src/gallium/drivers/freedreno/a4xx/fd4_gmem.c | 2 +-
src/gallium/drivers/freedreno/a5xx/fd5_gmem.c | 2 +-
src/gallium/drivers/freedreno/a6xx/fd6_gmem.c | 4 ++--
5 files changed, 12 insertions(+), 12 deletions(-)
diff --git a/src/gallium/drivers/freedreno/a2xx/fd2_gmem.c
b/src/gallium/drivers/freedreno/a2xx/fd2_gmem.c
index 0c7ea844fa4..0edc5e940c1 100644
--- a/src/gallium/drivers/freedreno/a2xx/fd2_gmem.c
+++ b/src/gallium/drivers/freedreno/a2xx/fd2_gmem.c
@@ -397,21 +397,21 @@ static void
patch_draws(struct fd_batch *batch, enum pc_di_vis_cull_mode vismode)
{
unsigned i;
if (!is_a20x(batch->ctx->screen)) {
/* identical to a3xx */
for (i = 0; i < fd_patch_num_elements(&batch->draw_patches);
i++) {
struct fd_cs_patch *patch =
fd_patch_element(&batch->draw_patches, i);
*patch->cs = patch->val | DRAW(0, 0, 0, vismode, 0);
}
- util_dynarray_resize(&batch->draw_patches, 0);
+ util_dynarray_clear(&batch->draw_patches);
return;
}
if (vismode == USE_VISIBILITY)
return;
for (i = 0; i < batch->draw_patches.size / sizeof(uint32_t*); i++) {
uint32_t *ptr = *util_dynarray_element(&batch->draw_patches,
uint32_t*, i);
unsigned cnt = ptr[0] >> 16 & 0xfff; /* 5 with idx buffer, 3
without */
@@ -465,22 +465,22 @@ fd2_emit_sysmem_prep(struct fd_batch *batch)
OUT_RING(ring, A2XX_PA_SC_SCREEN_SCISSOR_TL_WINDOW_OFFSET_DISABLE);
OUT_RING(ring, A2XX_PA_SC_SCREEN_SCISSOR_BR_X(pfb->width) |
A2XX_PA_SC_SCREEN_SCISSOR_BR_Y(pfb->height));
OUT_PKT3(ring, CP_SET_CONSTANT, 2);
OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_WINDOW_OFFSET));
OUT_RING(ring, A2XX_PA_SC_WINDOW_OFFSET_X(0) |
A2XX_PA_SC_WINDOW_OFFSET_Y(0));
patch_draws(batch, IGNORE_VISIBILITY);
- util_dynarray_resize(&batch->draw_patches, 0);
- util_dynarray_resize(&batch->shader_patches, 0);
+ util_dynarray_clear(&batch->draw_patches);
+ util_dynarray_clear(&batch->shader_patches);
}
/* before first tile */
static void
fd2_emit_tile_init(struct fd_batch *batch)
{
struct fd_context *ctx = batch->ctx;
struct fd_ringbuffer *ring = batch->gmem;
struct pipe_framebuffer_state *pfb = &batch->framebuffer;
struct fd_gmem_stateobj *gmem = &ctx->gmem;
@@ -544,21 +544,21 @@ fd2_emit_tile_init(struct fd_batch *batch)
continue;
}
patch->cs[0] = A2XX_PA_SC_SCREEN_SCISSOR_BR_X(32) |
A2XX_PA_SC_SCREEN_SCISSOR_BR_Y(lines);
patch->cs[4] = A2XX_RB_COLOR_INFO_BASE(color_base) |
A2XX_RB_COLOR_INFO_FORMAT(COLORX_8_8_8_8);
patch->cs[5] = A2XX_RB_DEPTH_INFO_DEPTH_BASE(depth_base) |
A2XX_RB_DEPTH_INFO_DEPTH_FORMAT(1);
}
- util_dynarray_resize(&batch->gmem_patches, 0);
+ util_dynarray_clear(&batch->gmem_patches);
/* set to zero, for some reason hardware doesn't like certain values */
OUT_PKT3(ring, CP_SET_CONSTANT, 2);
OUT_RING(ring, CP_REG(REG_A2XX_VGT_CURRENT_BIN_ID_MIN));
OUT_RING(ring, 0);
OUT_PKT3(ring, CP_SET_CONSTANT, 2);
OUT_RING(ring, CP_REG(REG_A2XX_VGT_CURRENT_BIN_ID_MAX));
OUT_RING(ring, 0);
@@ -649,22 +649,22 @@ fd2_emit_tile_init(struct fd_batch *batch)
ctx->emit_ib(ring, batch->binning);
OUT_PKT3(ring, CP_SET_CONSTANT, 2);
OUT_RING(ring, CP_REG(REG_A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL));
OUT_RING(ring, 0x00000002);
} else {
patch_draws(batch, IGNORE_VISIBILITY);
}
- util_dynarray_resize(&batch->draw_patches, 0);
- util_dynarray_resize(&batch->shader_patches, 0);
+ util_dynarray_clear(&batch->draw_patches);
+ util_dynarray_clear(&batch->shader_patches);
}
/* before mem2gmem */
static void
fd2_emit_tile_prep(struct fd_batch *batch, struct fd_tile *tile)
{
struct fd_ringbuffer *ring = batch->gmem;
struct pipe_framebuffer_state *pfb = &batch->framebuffer;
enum pipe_format format = pipe_surface_format(pfb->cbufs[0]);
diff --git a/src/gallium/drivers/freedreno/a3xx/fd3_gmem.c
b/src/gallium/drivers/freedreno/a3xx/fd3_gmem.c
index 7de0a92cdc1..e4455b3fa63 100644
--- a/src/gallium/drivers/freedreno/a3xx/fd3_gmem.c
+++ b/src/gallium/drivers/freedreno/a3xx/fd3_gmem.c
@@ -704,32 +704,32 @@ fd3_emit_tile_mem2gmem(struct fd_batch *batch, struct
fd_tile *tile)
}
static void
patch_draws(struct fd_batch *batch, enum pc_di_vis_cull_mode vismode)
{
unsigned i;
for (i = 0; i < fd_patch_num_elements(&batch->draw_patches); i++) {
struct fd_cs_patch *patch =
fd_patch_element(&batch->draw_patches, i);
*patch->cs = patch->val | DRAW(0, 0, 0, vismode, 0);
}
- util_dynarray_resize(&batch->draw_patches, 0);
+ util_dynarray_clear(&batch->draw_patches);
}
static void
patch_rbrc(struct fd_batch *batch, uint32_t val)
{
unsigned i;
for (i = 0; i < fd_patch_num_elements(&batch->rbrc_patches); i++) {
struct fd_cs_patch *patch =
fd_patch_element(&batch->rbrc_patches, i);
*patch->cs = patch->val | val;
}
- util_dynarray_resize(&batch->rbrc_patches, 0);
+ util_dynarray_clear(&batch->rbrc_patches);
}
/* for rendering directly to system memory: */
static void
fd3_emit_sysmem_prep(struct fd_batch *batch)
{
struct pipe_framebuffer_state *pfb = &batch->framebuffer;
struct fd_ringbuffer *ring = batch->gmem;
uint32_t i, pitch = 0;
diff --git a/src/gallium/drivers/freedreno/a4xx/fd4_gmem.c
b/src/gallium/drivers/freedreno/a4xx/fd4_gmem.c
index 7543658dc08..2c5e1f5850e 100644
--- a/src/gallium/drivers/freedreno/a4xx/fd4_gmem.c
+++ b/src/gallium/drivers/freedreno/a4xx/fd4_gmem.c
@@ -510,21 +510,21 @@ fd4_emit_tile_mem2gmem(struct fd_batch *batch, struct
fd_tile *tile)
}
static void
patch_draws(struct fd_batch *batch, enum pc_di_vis_cull_mode vismode)
{
unsigned i;
for (i = 0; i < fd_patch_num_elements(&batch->draw_patches); i++) {
struct fd_cs_patch *patch =
fd_patch_element(&batch->draw_patches, i);
*patch->cs = patch->val | DRAW4(0, 0, 0, vismode);
}
- util_dynarray_resize(&batch->draw_patches, 0);
+ util_dynarray_clear(&batch->draw_patches);
}
/* for rendering directly to system memory: */
static void
fd4_emit_sysmem_prep(struct fd_batch *batch)
{
struct pipe_framebuffer_state *pfb = &batch->framebuffer;
struct fd_ringbuffer *ring = batch->gmem;
fd4_emit_restore(batch, ring);
diff --git a/src/gallium/drivers/freedreno/a5xx/fd5_gmem.c
b/src/gallium/drivers/freedreno/a5xx/fd5_gmem.c
index d72d36dde3e..c95acd66aef 100644
--- a/src/gallium/drivers/freedreno/a5xx/fd5_gmem.c
+++ b/src/gallium/drivers/freedreno/a5xx/fd5_gmem.c
@@ -248,21 +248,21 @@ use_hw_binning(struct fd_batch *batch)
}
static void
patch_draws(struct fd_batch *batch, enum pc_di_vis_cull_mode vismode)
{
unsigned i;
for (i = 0; i < fd_patch_num_elements(&batch->draw_patches); i++) {
struct fd_cs_patch *patch =
fd_patch_element(&batch->draw_patches, i);
*patch->cs = patch->val | DRAW4(0, 0, 0, vismode);
}
- util_dynarray_resize(&batch->draw_patches, 0);
+ util_dynarray_clear(&batch->draw_patches);
}
static void
update_vsc_pipe(struct fd_batch *batch)
{
struct fd_context *ctx = batch->ctx;
struct fd5_context *fd5_ctx = fd5_context(ctx);
struct fd_gmem_stateobj *gmem = &batch->ctx->gmem;
struct fd_ringbuffer *ring = batch->gmem;
int i;
diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_gmem.c
b/src/gallium/drivers/freedreno/a6xx/fd6_gmem.c
index a00e4446333..bc3526fa6ba 100644
--- a/src/gallium/drivers/freedreno/a6xx/fd6_gmem.c
+++ b/src/gallium/drivers/freedreno/a6xx/fd6_gmem.c
@@ -267,32 +267,32 @@ use_hw_binning(struct fd_batch *batch)
static void
patch_fb_read(struct fd_batch *batch)
{
struct fd_gmem_stateobj *gmem = &batch->ctx->gmem;
for (unsigned i = 0; i <
fd_patch_num_elements(&batch->fb_read_patches); i++) {
struct fd_cs_patch *patch =
fd_patch_element(&batch->fb_read_patches, i);
*patch->cs = patch->val | A6XX_TEX_CONST_2_PITCH(gmem->bin_w *
gmem->cbuf_cpp[0]);
}
- util_dynarray_resize(&batch->fb_read_patches, 0);
+ util_dynarray_clear(&batch->fb_read_patches);
}
static void
patch_draws(struct fd_batch *batch, enum pc_di_vis_cull_mode vismode)
{
unsigned i;
for (i = 0; i < fd_patch_num_elements(&batch->draw_patches); i++) {
struct fd_cs_patch *patch =
fd_patch_element(&batch->draw_patches, i);
*patch->cs = patch->val | DRAW4(0, 0, 0, vismode);
}
- util_dynarray_resize(&batch->draw_patches, 0);
+ util_dynarray_clear(&batch->draw_patches);
}
static void
update_render_cntl(struct fd_batch *batch, struct pipe_framebuffer_state *pfb,
bool binning)
{
struct fd_ringbuffer *ring = batch->gmem;
uint32_t cntl = 0;
bool depth_ubwc_enable = false;
uint32_t mrts_ubwc_enable = 0;
int i;
--
2.20.1
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