From: Marek Olšák <marek.ol...@amd.com>
it's the same design
---
include/pci_ids/radeonsi_pci_ids.h | 32 +++++++++----------
src/amd/common/ac_gpu_info.c | 2 --
src/amd/common/ac_llvm_util.c | 2 --
src/amd/common/ac_surface.c | 4 ---
src/amd/common/amd_family.h | 1 -
src/amd/vulkan/radv_device.c | 1 -
src/amd/vulkan/radv_pipeline.c | 3 +-
src/gallium/drivers/radeonsi/cik_sdma.c | 6 ++--
src/gallium/drivers/radeonsi/si_shader.c | 3 +-
.../winsys/radeon/drm/radeon_drm_winsys.c | 3 --
10 files changed, 20 insertions(+), 37 deletions(-)
diff --git a/include/pci_ids/radeonsi_pci_ids.h
b/include/pci_ids/radeonsi_pci_ids.h
index 75ac7761bb4..65ae163f231 100644
--- a/include/pci_ids/radeonsi_pci_ids.h
+++ b/include/pci_ids/radeonsi_pci_ids.h
@@ -98,36 +98,36 @@ CHIPSET(0x9836, KABINI)
CHIPSET(0x9837, KABINI)
CHIPSET(0x9838, KABINI)
CHIPSET(0x9839, KABINI)
CHIPSET(0x983A, KABINI)
CHIPSET(0x983B, KABINI)
CHIPSET(0x983C, KABINI)
CHIPSET(0x983D, KABINI)
CHIPSET(0x983E, KABINI)
CHIPSET(0x983F, KABINI)
-CHIPSET(0x9850, MULLINS)
-CHIPSET(0x9851, MULLINS)
-CHIPSET(0x9852, MULLINS)
-CHIPSET(0x9853, MULLINS)
-CHIPSET(0x9854, MULLINS)
-CHIPSET(0x9855, MULLINS)
-CHIPSET(0x9856, MULLINS)
-CHIPSET(0x9857, MULLINS)
-CHIPSET(0x9858, MULLINS)
-CHIPSET(0x9859, MULLINS)
-CHIPSET(0x985A, MULLINS)
-CHIPSET(0x985B, MULLINS)
-CHIPSET(0x985C, MULLINS)
-CHIPSET(0x985D, MULLINS)
-CHIPSET(0x985E, MULLINS)
-CHIPSET(0x985F, MULLINS)
+CHIPSET(0x9850, KABINI)
+CHIPSET(0x9851, KABINI)
+CHIPSET(0x9852, KABINI)
+CHIPSET(0x9853, KABINI)
+CHIPSET(0x9854, KABINI)
+CHIPSET(0x9855, KABINI)
+CHIPSET(0x9856, KABINI)
+CHIPSET(0x9857, KABINI)
+CHIPSET(0x9858, KABINI)
+CHIPSET(0x9859, KABINI)
+CHIPSET(0x985A, KABINI)
+CHIPSET(0x985B, KABINI)
+CHIPSET(0x985C, KABINI)
+CHIPSET(0x985D, KABINI)
+CHIPSET(0x985E, KABINI)
+CHIPSET(0x985F, KABINI)
CHIPSET(0x1304, KAVERI)
CHIPSET(0x1305, KAVERI)
CHIPSET(0x1306, KAVERI)
CHIPSET(0x1307, KAVERI)
CHIPSET(0x1309, KAVERI)
CHIPSET(0x130A, KAVERI)
CHIPSET(0x130B, KAVERI)
CHIPSET(0x130C, KAVERI)
CHIPSET(0x130D, KAVERI)
diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c
index 171560d6f04..fc3dfc951e3 100644
--- a/src/amd/common/ac_gpu_info.c
+++ b/src/amd/common/ac_gpu_info.c
@@ -640,21 +640,20 @@ int
ac_get_gs_table_depth(enum chip_class chip_class, enum radeon_family family)
{
if (chip_class >= GFX9)
return -1;
switch (family) {
case CHIP_OLAND:
case CHIP_HAINAN:
case CHIP_KAVERI:
case CHIP_KABINI:
- case CHIP_MULLINS:
case CHIP_ICELAND:
case CHIP_CARRIZO:
case CHIP_STONEY:
return 16;
case CHIP_TAHITI:
case CHIP_PITCAIRN:
case CHIP_VERDE:
case CHIP_BONAIRE:
case CHIP_HAWAII:
case CHIP_TONGA:
@@ -674,21 +673,20 @@ ac_get_raster_config(struct radeon_info *info,
uint32_t *raster_config_p,
uint32_t *raster_config_1_p,
uint32_t *se_tile_repeat_p)
{
unsigned raster_config, raster_config_1, se_tile_repeat;
switch (info->family) {
/* 1 SE / 1 RB */
case CHIP_HAINAN:
case CHIP_KABINI:
- case CHIP_MULLINS:
case CHIP_STONEY:
raster_config = 0x00000000;
raster_config_1 = 0x00000000;
break;
/* 1 SE / 4 RBs */
case CHIP_VERDE:
raster_config = 0x0000124a;
raster_config_1 = 0x00000000;
break;
/* 1 SE / 2 RBs (Oland is special) */
diff --git a/src/amd/common/ac_llvm_util.c b/src/amd/common/ac_llvm_util.c
index 69446863b95..a4e5ccb41da 100644
--- a/src/amd/common/ac_llvm_util.c
+++ b/src/amd/common/ac_llvm_util.c
@@ -100,22 +100,20 @@ const char *ac_get_llvm_processor_name(enum radeon_family
family)
case CHIP_HAINAN:
return "hainan";
case CHIP_BONAIRE:
return "bonaire";
case CHIP_KABINI:
return "kabini";
case CHIP_KAVERI:
return "kaveri";
case CHIP_HAWAII:
return "hawaii";
- case CHIP_MULLINS:
- return "mullins";
case CHIP_TONGA:
return "tonga";
case CHIP_ICELAND:
return "iceland";
case CHIP_CARRIZO:
return "carrizo";
case CHIP_FIJI:
return "fiji";
case CHIP_STONEY:
return "stoney";
diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c
index a9433b9696c..28256352cb7 100644
--- a/src/amd/common/ac_surface.c
+++ b/src/amd/common/ac_surface.c
@@ -88,24 +88,20 @@ static void addrlib_family_rev_id(enum radeon_family family,
*addrlib_revid = get_first(AMDGPU_SPECTRE_RANGE);
break;
case CHIP_KABINI:
*addrlib_family = FAMILY_KV;
*addrlib_revid = get_first(AMDGPU_KALINDI_RANGE);
break;
case CHIP_HAWAII:
*addrlib_family = FAMILY_CI;
*addrlib_revid = get_first(AMDGPU_HAWAII_RANGE);
break;
- case CHIP_MULLINS:
- *addrlib_family = FAMILY_KV;
- *addrlib_revid = get_first(AMDGPU_GODAVARI_RANGE);
- break;
case CHIP_TONGA:
*addrlib_family = FAMILY_VI;
*addrlib_revid = get_first(AMDGPU_TONGA_RANGE);
break;
case CHIP_ICELAND:
*addrlib_family = FAMILY_VI;
*addrlib_revid = get_first(AMDGPU_ICELAND_RANGE);
break;
case CHIP_CARRIZO:
*addrlib_family = FAMILY_CZ;
diff --git a/src/amd/common/amd_family.h b/src/amd/common/amd_family.h
index ee30dc74b93..acc7673bee1 100644
--- a/src/amd/common/amd_family.h
+++ b/src/amd/common/amd_family.h
@@ -76,21 +76,20 @@ enum radeon_family {
CHIP_ARUBA,
CHIP_TAHITI, /* GFX6 (Southern Islands) */
CHIP_PITCAIRN,
CHIP_VERDE,
CHIP_OLAND,
CHIP_HAINAN,
CHIP_BONAIRE, /* GFX7 (Sea Islands) */
CHIP_KAVERI,
CHIP_KABINI,
CHIP_HAWAII,
- CHIP_MULLINS,
CHIP_TONGA, /* GFX8 (Volcanic Islands & Polaris) */
CHIP_ICELAND,
CHIP_CARRIZO,
CHIP_FIJI,
CHIP_STONEY,
CHIP_POLARIS10,
CHIP_POLARIS11,
CHIP_POLARIS12,
CHIP_VEGAM,
CHIP_VEGA10, /* GFX9 (Vega) */
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index c0e317a97e5..ecdcf02c9de 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -93,21 +93,20 @@ radv_get_device_name(enum radeon_family family, char *name,
size_t name_len)
switch (family) {
case CHIP_TAHITI: chip_string = "AMD RADV TAHITI"; break;
case CHIP_PITCAIRN: chip_string = "AMD RADV PITCAIRN"; break;
case CHIP_VERDE: chip_string = "AMD RADV CAPE VERDE"; break;
case CHIP_OLAND: chip_string = "AMD RADV OLAND"; break;
case CHIP_HAINAN: chip_string = "AMD RADV HAINAN"; break;
case CHIP_BONAIRE: chip_string = "AMD RADV BONAIRE"; break;
case CHIP_KAVERI: chip_string = "AMD RADV KAVERI"; break;
case CHIP_KABINI: chip_string = "AMD RADV KABINI"; break;
case CHIP_HAWAII: chip_string = "AMD RADV HAWAII"; break;
- case CHIP_MULLINS: chip_string = "AMD RADV MULLINS"; break;
case CHIP_TONGA: chip_string = "AMD RADV TONGA"; break;
case CHIP_ICELAND: chip_string = "AMD RADV ICELAND"; break;
case CHIP_CARRIZO: chip_string = "AMD RADV CARRIZO"; break;
case CHIP_FIJI: chip_string = "AMD RADV FIJI"; break;
case CHIP_POLARIS10: chip_string = "AMD RADV POLARIS10"; break;
case CHIP_POLARIS11: chip_string = "AMD RADV POLARIS11"; break;
case CHIP_POLARIS12: chip_string = "AMD RADV POLARIS12"; break;
case CHIP_STONEY: chip_string = "AMD RADV STONEY"; break;
case CHIP_VEGAM: chip_string = "AMD RADV VEGA M"; break;
case CHIP_VEGA10: chip_string = "AMD RADV VEGA10"; break;
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index c89a6f139ba..5d523a41600 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -1593,22 +1593,21 @@ static void si_multiwave_lds_size_workaround(struct
radv_device *device,
/* If tessellation is all offchip and on-chip GS isn't used, this
* workaround is not needed.
*/
return;
/* SPI barrier management bug:
* Make sure we have at least 4k of LDS in use to avoid the bug.
* It applies to workgroup sizes of more than one wavefront.
*/
if (device->physical_device->rad_info.family == CHIP_BONAIRE ||
- device->physical_device->rad_info.family == CHIP_KABINI ||
- device->physical_device->rad_info.family == CHIP_MULLINS)
+ device->physical_device->rad_info.family == CHIP_KABINI)
*lds_size = MAX2(*lds_size, 8);
}
struct radv_shader_variant *
radv_get_shader(struct radv_pipeline *pipeline,
gl_shader_stage stage)
{
if (stage == MESA_SHADER_VERTEX) {
if (pipeline->shaders[MESA_SHADER_VERTEX])
return pipeline->shaders[MESA_SHADER_VERTEX];
diff --git a/src/gallium/drivers/radeonsi/cik_sdma.c
b/src/gallium/drivers/radeonsi/cik_sdma.c
index 2728541dd29..ba62295318f 100644
--- a/src/gallium/drivers/radeonsi/cik_sdma.c
+++ b/src/gallium/drivers/radeonsi/cik_sdma.c
@@ -265,22 +265,21 @@ static bool cik_sdma_copy_texture(struct si_context *sctx,
return false;
if (sctx->chip_class == GFX7 &&
(copy_width_aligned == (1 << 14) ||
copy_height == (1 << 14) ||
copy_depth == (1 << 11)))
return false;
if ((sctx->family == CHIP_BONAIRE ||
sctx->family == CHIP_KAVERI ||
- sctx->family == CHIP_KABINI ||
- sctx->family == CHIP_MULLINS) &&
+ sctx->family == CHIP_KABINI) &&
(tiled_x + copy_width == (1 << 14) ||
tiled_y + copy_height == (1 << 14)))
return false;
/* The hw can read outside of the given linear buffer bounds,
* or access those pages but not touch the memory in case
* of writes. (it still causes a VM fault)
*
* Out-of-bounds memory access or page directory access must
* be prevented.
@@ -435,22 +434,21 @@ static bool cik_sdma_copy_texture(struct si_context *sctx,
copy_width_aligned % 8 == 0 &&
copy_height_aligned % 8 == 0 &&
/* HW limitation - GFX7: */
(sctx->chip_class != GFX7 ||
(copy_width_aligned < (1 << 14) &&
copy_height_aligned < (1 << 14) &&
copy_depth < (1 << 11))) &&
/* HW limitation - some GFX7 parts: */
((sctx->family != CHIP_BONAIRE &&
sctx->family != CHIP_KAVERI &&
- sctx->family != CHIP_KABINI &&
- sctx->family != CHIP_MULLINS) ||
+ sctx->family != CHIP_KABINI) ||
(srcx + copy_width_aligned != (1 << 14) &&
srcy + copy_height_aligned != (1 << 14) &&
dstx + copy_width != (1 << 14)))) {
struct radeon_cmdbuf *cs = sctx->dma_cs;
si_need_dma_space(sctx, 15, &sdst->buffer,
&ssrc->buffer);
radeon_emit(cs, CIK_SDMA_PACKET(CIK_SDMA_OPCODE_COPY,
CIK_SDMA_COPY_SUB_OPCODE_T2T_SUB_WINDOW, 0));
radeon_emit(cs, src_address);
diff --git a/src/gallium/drivers/radeonsi/si_shader.c
b/src/gallium/drivers/radeonsi/si_shader.c
index 98c11e1c98d..fc0a44cb344 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -7834,22 +7834,21 @@ void si_multiwave_lds_size_workaround(struct si_screen
*sscreen,
/* If tessellation is all offchip and on-chip GS isn't used, this
* workaround is not needed.
*/
return;
/* SPI barrier management bug:
* Make sure we have at least 4k of LDS in use to avoid the bug.
* It applies to workgroup sizes of more than one wavefront.
*/
if (sscreen->info.family == CHIP_BONAIRE ||
- sscreen->info.family == CHIP_KABINI ||
- sscreen->info.family == CHIP_MULLINS)
+ sscreen->info.family == CHIP_KABINI)
*lds_size = MAX2(*lds_size, 8);
}
static void si_fix_resource_usage(struct si_screen *sscreen,
struct si_shader *shader)
{
unsigned min_sgprs = shader->info.num_input_sgprs + 2; /* VCC */
shader->config.num_sgprs = MAX2(shader->config.num_sgprs, min_sgprs);
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
index 99ecbea283b..7aa45b52639 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
@@ -268,42 +268,40 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws)
case CHIP_PITCAIRN:
case CHIP_VERDE:
case CHIP_OLAND:
case CHIP_HAINAN:
ws->info.chip_class = GFX6;
break;
case CHIP_BONAIRE:
case CHIP_KAVERI:
case CHIP_KABINI:
case CHIP_HAWAII:
- case CHIP_MULLINS:
ws->info.chip_class = GFX7;
break;
}
/* Set which chips don't have dedicated VRAM. */
switch (ws->info.family) {
case CHIP_RS400:
case CHIP_RC410:
case CHIP_RS480:
case CHIP_RS600:
case CHIP_RS690:
case CHIP_RS740:
case CHIP_RS780:
case CHIP_RS880:
case CHIP_PALM:
case CHIP_SUMO:
case CHIP_SUMO2:
case CHIP_ARUBA:
case CHIP_KAVERI:
case CHIP_KABINI:
- case CHIP_MULLINS:
ws->info.has_dedicated_vram = false;
break;
default:
ws->info.has_dedicated_vram = true;
}
/* Check for dma */
ws->info.num_sdma_rings = 0;
/* DMA is disabled on R700. There is IB corruption and hangs. */
@@ -475,21 +473,20 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws)
ws->info.num_good_compute_units = 1;
radeon_get_drm_value(ws->fd, RADEON_INFO_ACTIVE_CU_COUNT, NULL,
&ws->info.num_good_compute_units);
radeon_get_drm_value(ws->fd, RADEON_INFO_MAX_SE, NULL,
&ws->info.max_se);
switch (ws->info.family) {
case CHIP_HAINAN:
case CHIP_KABINI:
- case CHIP_MULLINS:
ws->info.num_tcc_blocks = 2;
break;
case CHIP_VERDE:
case CHIP_OLAND:
case CHIP_BONAIRE:
case CHIP_KAVERI:
ws->info.num_tcc_blocks = 4;
break;
case CHIP_PITCAIRN:
ws->info.num_tcc_blocks = 8;
--
2.17.1
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