Patch Series Reviewed-By: Ryan Houdek <sonicadvan...@gmail.com> On Sat, May 25, 2019 at 7:39 PM Alyssa Rosenzweig <aly...@rosenzweig.io> wrote:
> This fairly-lengthy series is focused on improving the register > allocator and by extension the performance of the generated code. > Meanwhile, we cleanup the compiler, refactoring as we go, driven by the > overall arc of the RA improvements. I was particularly motivated by the > concerns raised by compiling code like: > > vec3 A = B * C; > float d = A.x * A.y; > > to something like > > vmul.fmul r0.xyz, [B], [C] > smul.fmul r1.x, r0.x, r0.y > > There are two clear problems here. One is that the r0.w component is > never used, but r1.x is -- doubling the register pressure from what it > needs to be, given register pressure is measured in vec4 for Midgard. On > many shaders, this affects the need to spill or number of threads > created. So the first half of the series, culminating in "Extend RA..." > would rewrite this code to use r0.w vs r1.x. > > The other is a bit more minor, but there's no need to use r0.x at all! > It turns out that within a VLIW bundle, we can push values directly > across, bypassing the register file, represented by the pseudo- pipeline > registers r24/r25. So by the improvements in the latter half of the > series, culminating in "Implement...", we instead get something like: > > vmul.fmul r24.xyz, [B], [C] > smul.fmul r0.x, r24.x, r24.y > > In addition to various stylistic cleanups, a major consequence of this > series is a unification of pre-schedule and post-schedule MIR. The > immediate effect is that our main work RA can now run post-schedule, > rather than just pre-schedule, without duplicating a whole bunch of > code. This will become particularly important as we want to balance > pipeline register creation with having to implement spilling eventually. > > Alyssa Rosenzweig (13): > panfrost/midgard: Remove pinning > panfrost/midgard: Share some utility functions > panfrost/midgard: Set int outmod for "pasted" code > panfrost/midgard: Fix liveness analysis bugs > panfrost/midgard: Set masks on ld_vary > panfrost/midgard: Extend RA to non-vec4 sources > panfrost/midgard: Misc. cleanup for readibility > panfrost/midgard: Refactor schedule/emit pipeline > panfrost/midgard: Add MIR helpers > panfrost/midgard: Implement "pipeline register" prepass > panfrost/midgard: Cleanup copy propagation > panfrost/midgard: Remove r0 scheduling code > panfrost/midgard: .pos propagation > > src/gallium/drivers/panfrost/meson.build | 4 + > .../drivers/panfrost/midgard/compiler.h | 117 ++- > .../drivers/panfrost/midgard/helpers.h | 73 ++ > .../panfrost/midgard/midgard_compile.c | 937 ++---------------- > .../drivers/panfrost/midgard/midgard_emit.c | 229 +++++ > .../panfrost/midgard/midgard_liveness.c | 10 +- > .../drivers/panfrost/midgard/midgard_ops.h | 21 + > .../drivers/panfrost/midgard/midgard_ra.c | 387 ++++++-- > .../panfrost/midgard/midgard_ra_pipeline.c | 87 ++ > .../panfrost/midgard/midgard_schedule.c | 425 ++++++++ > src/gallium/drivers/panfrost/midgard/mir.c | 53 + > 11 files changed, 1389 insertions(+), 954 deletions(-) > create mode 100644 src/gallium/drivers/panfrost/midgard/midgard_emit.c > create mode 100644 > src/gallium/drivers/panfrost/midgard/midgard_ra_pipeline.c > create mode 100644 src/gallium/drivers/panfrost/midgard/midgard_schedule.c > create mode 100644 src/gallium/drivers/panfrost/midgard/mir.c > > -- > 2.20.1 > >
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