Reviewed-by: Samuel Pitoiset <[email protected]>
On 6/5/19 5:09 PM, Connor Abbott wrote:
While we're here, copy the comment explaining this from radeonsi. --- src/amd/common/ac_nir_to_llvm.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c index 833b1e54abc..11de22a8cbd 100644 --- a/src/amd/common/ac_nir_to_llvm.c +++ b/src/amd/common/ac_nir_to_llvm.c @@ -3878,7 +3878,13 @@ static void visit_tex(struct ac_nir_context *ctx, nir_tex_instr *instr) args.offset = NULL; }- /* TODO TG4 support */+ /* DMASK was repurposed for GATHER4. 4 components are always + * returned and DMASK works like a swizzle - it selects + * the component to fetch. The only valid DMASK values are + * 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns + * (red,red,red,red) etc.) The ISA document doesn't mention + * this. + */ args.dmask = 0xf; if (instr->op == nir_texop_tg4) { if (instr->is_shadow)
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