From: Marek Olšák <marek.ol...@amd.com>
---
src/amd/common/ac_gpu_info.c | 2 +
src/amd/common/ac_gpu_info.h | 2 +
src/amd/common/ac_surface.c | 111 +----------------------------------
3 files changed, 7 insertions(+), 108 deletions(-)
diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c
index 4de6882f15e..cd81c5757f3 100644
--- a/src/amd/common/ac_gpu_info.c
+++ b/src/amd/common/ac_gpu_info.c
@@ -328,20 +328,22 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
info->chip_class = GFX8;
else if (info->family >= CHIP_BONAIRE)
info->chip_class = GFX7;
else if (info->family >= CHIP_TAHITI)
info->chip_class = GFX6;
else {
fprintf(stderr, "amdgpu: Unknown family.\n");
return false;
}
+ info->family_id = amdinfo->family_id;
+ info->chip_external_rev = amdinfo->chip_external_rev;
info->marketing_name = amdgpu_get_marketing_name(dev);
info->is_pro_graphics = info->marketing_name &&
(!strcmp(info->marketing_name, "Pro") ||
!strcmp(info->marketing_name, "PRO") ||
!strcmp(info->marketing_name, "Frontier"));
/* Set which chips have dedicated VRAM. */
info->has_dedicated_vram =
!(amdinfo->ids_flags & AMDGPU_IDS_FLAGS_FUSION);
diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h
index 2c67cec3ed5..d296c7eb89f 100644
--- a/src/amd/common/ac_gpu_info.h
+++ b/src/amd/common/ac_gpu_info.h
@@ -46,20 +46,22 @@ struct radeon_info {
uint32_t pci_dev;
uint32_t pci_func;
/* Device info. */
const char *name;
const char *marketing_name;
bool is_pro_graphics;
uint32_t pci_id;
enum radeon_family family;
enum chip_class chip_class;
+ uint32_t family_id;
+ uint32_t chip_external_rev;
uint32_t num_compute_rings;
uint32_t num_sdma_rings;
uint32_t clock_crystal_freq;
uint32_t tcc_cache_line_size;
/* There are 2 display DCC codepaths, because display expects unaligned
DCC. */
/* Disable RB and pipe alignment to skip the retile blit. (1 RB chips
only) */
bool use_display_dcc_unaligned;
/* Allocate both aligned and unaligned DCC and use the retile blit. */
bool use_display_dcc_with_retile_blit;
diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c
index 7b86cb1e1f2..b336655a913 100644
--- a/src/amd/common/ac_surface.c
+++ b/src/amd/common/ac_surface.c
@@ -42,127 +42,20 @@
#include "addrlib/inc/addrinterface.h"
#ifndef CIASICIDGFXENGINE_SOUTHERNISLAND
#define CIASICIDGFXENGINE_SOUTHERNISLAND 0x0000000A
#endif
#ifndef CIASICIDGFXENGINE_ARCTICISLAND
#define CIASICIDGFXENGINE_ARCTICISLAND 0x0000000D
#endif
-static unsigned get_first(unsigned x, unsigned y)
-{
- return x;
-}
-
-static void addrlib_family_rev_id(enum radeon_family family,
- unsigned *addrlib_family,
- unsigned *addrlib_revid)
-{
- switch (family) {
- case CHIP_TAHITI:
- *addrlib_family = FAMILY_SI;
- *addrlib_revid = get_first(AMDGPU_TAHITI_RANGE);
- break;
- case CHIP_PITCAIRN:
- *addrlib_family = FAMILY_SI;
- *addrlib_revid = get_first(AMDGPU_PITCAIRN_RANGE);
- break;
- case CHIP_VERDE:
- *addrlib_family = FAMILY_SI;
- *addrlib_revid = get_first(AMDGPU_CAPEVERDE_RANGE);
- break;
- case CHIP_OLAND:
- *addrlib_family = FAMILY_SI;
- *addrlib_revid = get_first(AMDGPU_OLAND_RANGE);
- break;
- case CHIP_HAINAN:
- *addrlib_family = FAMILY_SI;
- *addrlib_revid = get_first(AMDGPU_HAINAN_RANGE);
- break;
- case CHIP_BONAIRE:
- *addrlib_family = FAMILY_CI;
- *addrlib_revid = get_first(AMDGPU_BONAIRE_RANGE);
- break;
- case CHIP_KAVERI:
- *addrlib_family = FAMILY_KV;
- *addrlib_revid = get_first(AMDGPU_SPECTRE_RANGE);
- break;
- case CHIP_KABINI:
- *addrlib_family = FAMILY_KV;
- *addrlib_revid = get_first(AMDGPU_KALINDI_RANGE);
- break;
- case CHIP_HAWAII:
- *addrlib_family = FAMILY_CI;
- *addrlib_revid = get_first(AMDGPU_HAWAII_RANGE);
- break;
- case CHIP_TONGA:
- *addrlib_family = FAMILY_VI;
- *addrlib_revid = get_first(AMDGPU_TONGA_RANGE);
- break;
- case CHIP_ICELAND:
- *addrlib_family = FAMILY_VI;
- *addrlib_revid = get_first(AMDGPU_ICELAND_RANGE);
- break;
- case CHIP_CARRIZO:
- *addrlib_family = FAMILY_CZ;
- *addrlib_revid = get_first(AMDGPU_CARRIZO_RANGE);
- break;
- case CHIP_STONEY:
- *addrlib_family = FAMILY_CZ;
- *addrlib_revid = get_first(AMDGPU_STONEY_RANGE);
- break;
- case CHIP_FIJI:
- *addrlib_family = FAMILY_VI;
- *addrlib_revid = get_first(AMDGPU_FIJI_RANGE);
- break;
- case CHIP_POLARIS10:
- *addrlib_family = FAMILY_VI;
- *addrlib_revid = get_first(AMDGPU_POLARIS10_RANGE);
- break;
- case CHIP_POLARIS11:
- *addrlib_family = FAMILY_VI;
- *addrlib_revid = get_first(AMDGPU_POLARIS11_RANGE);
- break;
- case CHIP_POLARIS12:
- *addrlib_family = FAMILY_VI;
- *addrlib_revid = get_first(AMDGPU_POLARIS12_RANGE);
- break;
- case CHIP_VEGAM:
- *addrlib_family = FAMILY_VI;
- *addrlib_revid = get_first(AMDGPU_VEGAM_RANGE);
- break;
- case CHIP_VEGA10:
- *addrlib_family = FAMILY_AI;
- *addrlib_revid = get_first(AMDGPU_VEGA10_RANGE);
- break;
- case CHIP_VEGA12:
- *addrlib_family = FAMILY_AI;
- *addrlib_revid = get_first(AMDGPU_VEGA12_RANGE);
- break;
- case CHIP_VEGA20:
- *addrlib_family = FAMILY_AI;
- *addrlib_revid = get_first(AMDGPU_VEGA20_RANGE);
- break;
- case CHIP_RAVEN:
- *addrlib_family = FAMILY_RV;
- *addrlib_revid = get_first(AMDGPU_RAVEN_RANGE);
- break;
- case CHIP_RAVEN2:
- *addrlib_family = FAMILY_RV;
- *addrlib_revid = get_first(AMDGPU_RAVEN2_RANGE);
- break;
- default:
- fprintf(stderr, "amdgpu: Unknown family.\n");
- }
-}
-
static void *ADDR_API allocSysMem(const ADDR_ALLOCSYSMEM_INPUT * pInput)
{
return malloc(pInput->sizeInBytes);
}
static ADDR_E_RETURNCODE ADDR_API freeSysMem(const ADDR_FREESYSMEM_INPUT *
pInput)
{
free(pInput->pVirtAddr);
return ADDR_OK;
}
@@ -177,21 +70,23 @@ ADDR_HANDLE amdgpu_addr_create(const struct radeon_info
*info,
ADDR_CREATE_FLAGS createFlags = {{0}};
ADDR_GET_MAX_ALINGMENTS_OUTPUT addrGetMaxAlignmentsOutput = {0};
ADDR_E_RETURNCODE addrRet;
addrCreateInput.size = sizeof(ADDR_CREATE_INPUT);
addrCreateOutput.size = sizeof(ADDR_CREATE_OUTPUT);
regValue.gbAddrConfig = amdinfo->gb_addr_cfg;
createFlags.value = 0;
- addrlib_family_rev_id(info->family, &addrCreateInput.chipFamily,
&addrCreateInput.chipRevision);
+ addrCreateInput.chipFamily = info->family_id;
+ addrCreateInput.chipRevision = info->chip_external_rev;
+
if (addrCreateInput.chipFamily == FAMILY_UNKNOWN)
return NULL;
if (addrCreateInput.chipFamily >= FAMILY_AI) {
addrCreateInput.chipEngine = CIASICIDGFXENGINE_ARCTICISLAND;
regValue.blockVarSizeLog2 = 0;
} else {
regValue.noOfBanks = amdinfo->mc_arb_ramcfg & 0x3;
regValue.noOfRanks = (amdinfo->mc_arb_ramcfg & 0x4) >> 2;
--
2.17.1
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