Signed-off-by: Samuel Pitoiset <[email protected]>
---
src/amd/common/ac_surface.c | 25 +++++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c
index 9e45bd44b72..cc4aea5f8d9 100644
--- a/src/amd/common/ac_surface.c
+++ b/src/amd/common/ac_surface.c
@@ -308,6 +308,31 @@ static int gfx6_compute_level(ADDR_HANDLE addrlib,
* slice is the same size) it's easy to compute.
*/
surf->dcc_slice_size = AddrDccOut->dccRamSize /
config->info.array_size;
+
+ /* For arrays, we have to compute the DCC info again
+ * with one slice size to get a correct fast clear
+ * size.
+ */
+ if (config->info.array_size > 1) {
+ AddrDccIn->colorSurfSize =
AddrSurfInfoOut->sliceSize;
+ AddrDccIn->tileMode = AddrSurfInfoOut->tileMode;
+ AddrDccIn->tileInfo =
*AddrSurfInfoOut->pTileInfo;
+ AddrDccIn->tileIndex =
AddrSurfInfoOut->tileIndex;
+ AddrDccIn->macroModeIndex =
AddrSurfInfoOut->macroModeIndex;
+
+ ret = AddrComputeDccInfo(addrlib,
+ AddrDccIn, AddrDccOut);
+ if (ret == ADDR_OK) {
+ /* If the DCC memory isn't properly
+ * aligned, the data are interleaved
+ * accross slices.
+ */
+ if (AddrDccOut->dccRamSizeAligned)
+ surf_level->dcc_fast_clear_size
= AddrDccOut->dccFastClearSize;
+ else
+ surf_level->dcc_fast_clear_size
= 0;
+ }
+ }
}
}
--
2.22.0
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