Cleanup.
Signed-off-by: Samuel Pitoiset <[email protected]>
---
src/amd/vulkan/radv_cmd_buffer.c | 75 +++++++++++++++-----------------
src/amd/vulkan/radv_private.h | 1 +
2 files changed, 37 insertions(+), 39 deletions(-)
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index dacd8c8d803..49d2f1e82bb 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -233,7 +233,7 @@ radv_bind_streamout_state(struct radv_cmd_buffer
*cmd_buffer,
bool radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)
{
return cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE &&
- cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;
+ cmd_buffer->info->chip_class >= GFX7;
}
enum ring_type radv_queue_family_to_ring(int f) {
@@ -264,6 +264,7 @@ static VkResult radv_create_cmd_buffer(
cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
cmd_buffer->device = device;
+ cmd_buffer->info = &device->physical_device->rad_info;
cmd_buffer->pool = pool;
cmd_buffer->level = level;
@@ -351,9 +352,9 @@ radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
cmd_buffer->descriptors[i].push_dirty = false;
}
- if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 &&
+ if (cmd_buffer->info->chip_class >= GFX9 &&
cmd_buffer->queue_family_index == RADV_QUEUE_GENERAL) {
- unsigned num_db =
cmd_buffer->device->physical_device->rad_info.num_render_backends;
+ unsigned num_db = cmd_buffer->info->num_render_backends;
unsigned fence_offset, eop_bug_offset;
void *fence_ptr;
@@ -518,7 +519,7 @@ radv_cmd_buffer_after_draw(struct radv_cmd_buffer
*cmd_buffer,
/* Force wait for graphics or compute engines to be idle. */
si_cs_emit_cache_flush(cmd_buffer->cs,
-
cmd_buffer->device->physical_device->rad_info.chip_class,
+ cmd_buffer->info->chip_class,
&cmd_buffer->gfx9_fence_idx,
cmd_buffer->gfx9_fence_va,
radv_cmd_buffer_uses_mec(cmd_buffer),
@@ -1244,7 +1245,7 @@ radv_emit_fb_color_state(struct radv_cmd_buffer
*cmd_buffer,
struct radv_image_view *iview,
VkImageLayout layout)
{
- bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class
>= GFX8;
+ bool is_vi = cmd_buffer->info->chip_class >= GFX8;
struct radv_color_buffer_info *cb = &att->cb;
uint32_t cb_color_info = cb->cb_color_info;
struct radv_image *image = iview->image;
@@ -1265,7 +1266,7 @@ radv_emit_fb_color_state(struct radv_cmd_buffer
*cmd_buffer,
cb_color_info &= C_028C70_FMASK_COMPRESS_1FRAG_ONLY;
}
- if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
+ if (cmd_buffer->info->chip_class >= GFX10) {
radeon_set_context_reg_seq(cmd_buffer->cs,
R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
radeon_emit(cmd_buffer->cs, cb->cb_color_base);
radeon_emit(cmd_buffer->cs, 0);
@@ -1294,7 +1295,7 @@ radv_emit_fb_color_state(struct radv_cmd_buffer
*cmd_buffer,
cb->cb_color_attrib2);
radeon_set_context_reg(cmd_buffer->cs,
R_028EE0_CB_COLOR0_ATTRIB3 + index * 4,
cb->cb_color_attrib3);
- } else if (cmd_buffer->device->physical_device->rad_info.chip_class >=
GFX9) {
+ } else if (cmd_buffer->info->chip_class >= GFX9) {
radeon_set_context_reg_seq(cmd_buffer->cs,
R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
radeon_emit(cmd_buffer->cs, cb->cb_color_base);
radeon_emit(cmd_buffer->cs,
S_028C64_BASE_256B(cb->cb_color_base >> 32));
@@ -1368,7 +1369,7 @@ radv_update_zrange_precision(struct radv_cmd_buffer
*cmd_buffer,
db_z_info &= C_028040_ZRANGE_PRECISION;
- if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {
+ if (cmd_buffer->info->chip_class == GFX9) {
db_z_info_reg = R_028038_DB_Z_INFO;
} else {
db_z_info_reg = R_028040_DB_Z_INFO;
@@ -1412,7 +1413,7 @@ radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW,
ds->db_depth_view);
radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE,
ds->db_htile_surface);
- if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
+ if (cmd_buffer->info->chip_class >= GFX10) {
radeon_set_context_reg(cmd_buffer->cs,
R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);
radeon_set_context_reg(cmd_buffer->cs,
R_02801C_DB_DEPTH_SIZE_XY, ds->db_depth_size);
@@ -1431,7 +1432,7 @@ radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32);
radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32);
radeon_emit(cmd_buffer->cs, ds->db_htile_data_base >> 32);
- } else if (cmd_buffer->device->physical_device->rad_info.chip_class >=
GFX9) {
+ } else if (cmd_buffer->info->chip_class >= GFX9) {
radeon_set_context_reg_seq(cmd_buffer->cs,
R_028014_DB_HTILE_DATA_BASE, 3);
radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
radeon_emit(cmd_buffer->cs,
S_028018_BASE_HI(ds->db_htile_data_base >> 32));
@@ -1904,7 +1905,7 @@ radv_emit_framebuffer_state(struct radv_cmd_buffer
*cmd_buffer)
}
radv_load_ds_clear_metadata(cmd_buffer, image);
} else {
- if (cmd_buffer->device->physical_device->rad_info.chip_class ==
GFX9)
+ if (cmd_buffer->info->chip_class == GFX9)
radeon_set_context_reg_seq(cmd_buffer->cs,
R_028038_DB_Z_INFO, 2);
else
radeon_set_context_reg_seq(cmd_buffer->cs,
R_028040_DB_Z_INFO, 2);
@@ -1916,11 +1917,11 @@ radv_emit_framebuffer_state(struct radv_cmd_buffer
*cmd_buffer)
S_028208_BR_X(framebuffer->width) |
S_028208_BR_Y(framebuffer->height));
- if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8) {
+ if (cmd_buffer->info->chip_class >= GFX8) {
bool disable_constant_encode =
cmd_buffer->device->physical_device->has_dcc_constant_encode;
enum chip_class chip_class =
-
cmd_buffer->device->physical_device->rad_info.chip_class;
+ cmd_buffer->info->chip_class;
uint8_t watermark = chip_class >= GFX10 ? 6 : 4;
radeon_set_context_reg(cmd_buffer->cs, R_028424_CB_DCC_CONTROL,
@@ -1944,7 +1945,7 @@ radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer)
struct radv_cmd_state *state = &cmd_buffer->state;
if (state->index_type != state->last_index_type) {
- if (cmd_buffer->device->physical_device->rad_info.chip_class >=
GFX9) {
+ if (cmd_buffer->info->chip_class >= GFX9) {
radeon_set_uconfig_reg_idx(cmd_buffer->device->physical_device,
cs, R_03090C_VGT_INDEX_TYPE,
2, state->index_type);
@@ -1975,7 +1976,7 @@ void radv_set_db_count_control(struct radv_cmd_buffer
*cmd_buffer)
uint32_t db_count_control;
if(!cmd_buffer->state.active_occlusion_queries) {
- if (cmd_buffer->device->physical_device->rad_info.chip_class >=
GFX7) {
+ if (cmd_buffer->info->chip_class >= GFX7) {
if
(G_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(pa_sc_mode_cntl_1) &&
pipeline->graphics.disable_out_of_order_rast_for_occlusion &&
has_perfect_queries) {
@@ -1994,7 +1995,7 @@ void radv_set_db_count_control(struct radv_cmd_buffer
*cmd_buffer)
const struct radv_subpass *subpass = cmd_buffer->state.subpass;
uint32_t sample_rate = subpass ?
util_logbase2(subpass->max_sample_count) : 0;
- if (cmd_buffer->device->physical_device->rad_info.chip_class >=
GFX7) {
+ if (cmd_buffer->info->chip_class >= GFX7) {
db_count_control =
S_028004_PERFECT_ZPASS_COUNTS(has_perfect_queries) |
S_028004_SAMPLE_RATE(sample_rate) |
@@ -2306,7 +2307,7 @@ radv_flush_vertex_descriptors(struct radv_cmd_buffer
*cmd_buffer,
va += offset + buffer->offset;
desc[0] = va;
desc[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
S_008F04_STRIDE(stride);
- if
(cmd_buffer->device->physical_device->rad_info.chip_class <= GFX7 && stride)
+ if (cmd_buffer->info->chip_class <= GFX7 && stride)
desc[2] = (buffer->size - offset -
velems->format_size[i]) / stride + 1;
else
desc[2] = buffer->size - offset;
@@ -2315,7 +2316,7 @@ radv_flush_vertex_descriptors(struct radv_cmd_buffer
*cmd_buffer,
S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
- if
(cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
+ if (cmd_buffer->info->chip_class >= GFX10) {
desc[3] |=
S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_UINT) |
S_008F0C_OOB_SELECT(1) |
S_008F0C_RESOURCE_LEVEL(1);
@@ -2489,7 +2490,6 @@ si_emit_ia_multi_vgt_param(struct radv_cmd_buffer
*cmd_buffer,
bool count_from_stream_output,
uint32_t draw_vertex_count)
{
- struct radeon_info *info =
&cmd_buffer->device->physical_device->rad_info;
struct radv_cmd_state *state = &cmd_buffer->state;
struct radeon_cmdbuf *cs = cmd_buffer->cs;
unsigned ia_multi_vgt_param;
@@ -2501,12 +2501,12 @@ si_emit_ia_multi_vgt_param(struct radv_cmd_buffer
*cmd_buffer,
draw_vertex_count);
if (state->last_ia_multi_vgt_param != ia_multi_vgt_param) {
- if (info->chip_class >= GFX9) {
+ if (cmd_buffer->info->chip_class >= GFX9) {
radeon_set_uconfig_reg_idx(cmd_buffer->device->physical_device,
cs,
R_030960_IA_MULTI_VGT_PARAM,
4, ia_multi_vgt_param);
- } else if (info->chip_class >= GFX7) {
+ } else if (cmd_buffer->info->chip_class >= GFX7) {
radeon_set_context_reg_idx(cs,
R_028AA8_IA_MULTI_VGT_PARAM,
1, ia_multi_vgt_param);
@@ -2522,13 +2522,12 @@ static void
radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer,
const struct radv_draw_info *draw_info)
{
- struct radeon_info *info =
&cmd_buffer->device->physical_device->rad_info;
struct radv_cmd_state *state = &cmd_buffer->state;
struct radeon_cmdbuf *cs = cmd_buffer->cs;
int32_t primitive_reset_en;
/* Draw state. */
- if (info->chip_class < GFX10) {
+ if (cmd_buffer->info->chip_class < GFX10) {
si_emit_ia_multi_vgt_param(cmd_buffer,
draw_info->instance_count > 1,
draw_info->indirect,
!!draw_info->strmout_buffer,
@@ -2541,7 +2540,7 @@ radv_emit_draw_registers(struct radv_cmd_buffer
*cmd_buffer,
if (primitive_reset_en != state->last_primitive_reset_en) {
state->last_primitive_reset_en = primitive_reset_en;
- if (info->chip_class >= GFX9) {
+ if (cmd_buffer->info->chip_class >= GFX9) {
radeon_set_uconfig_reg(cs,
R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
primitive_reset_en);
@@ -2688,7 +2687,7 @@ radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
if (!radv_image_has_htile(image))
flush_DB_meta = false;
- if (cmd_buffer->device->physical_device->rad_info.chip_class >=
GFX9) {
+ if (cmd_buffer->info->chip_class >= GFX9) {
if (image->info.samples == 1 &&
(image->usage &
(VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT |
VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT)) &&
@@ -3262,7 +3261,7 @@ void radv_CmdBindDescriptorSets(
S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
- if
(cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
+ if (cmd_buffer->info->chip_class >= GFX10) {
dst[3] |=
S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
S_008F0C_OOB_SELECT(3) |
S_008F0C_RESOURCE_LEVEL(1);
@@ -3423,7 +3422,7 @@ VkResult radv_EndCommandBuffer(
RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
- if (cmd_buffer->device->physical_device->rad_info.chip_class ==
GFX6)
+ if (cmd_buffer->info->chip_class == GFX6)
cmd_buffer->state.flush_bits |=
RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
RADV_CMD_FLAG_WB_L2;
/* Make sure to sync all pending active queries at the end of
@@ -4331,7 +4330,7 @@ radv_emit_all_graphics_states(struct radv_cmd_buffer
*cmd_buffer,
* so the state must be re-emitted before the next indexed
* draw.
*/
- if (cmd_buffer->device->physical_device->rad_info.chip_class >=
GFX7) {
+ if (cmd_buffer->info->chip_class >= GFX7) {
cmd_buffer->state.last_index_type = -1;
cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;
}
@@ -4349,10 +4348,8 @@ static void
radv_draw(struct radv_cmd_buffer *cmd_buffer,
const struct radv_draw_info *info)
{
- struct radeon_info *rad_info =
- &cmd_buffer->device->physical_device->rad_info;
bool has_prefetch =
- cmd_buffer->device->physical_device->rad_info.chip_class >=
GFX7;
+ cmd_buffer->info->chip_class >= GFX7;
bool pipeline_is_dirty =
(cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) &&
cmd_buffer->state.pipeline !=
cmd_buffer->state.emitted_pipeline;
@@ -4437,9 +4434,9 @@ radv_draw(struct radv_cmd_buffer *cmd_buffer,
* It must be done after drawing.
*/
if (cmd_buffer->state.streamout.streamout_enabled &&
- (rad_info->family == CHIP_HAWAII ||
- rad_info->family == CHIP_TONGA ||
- rad_info->family == CHIP_FIJI)) {
+ (cmd_buffer->info->family == CHIP_HAWAII ||
+ cmd_buffer->info->family == CHIP_TONGA ||
+ cmd_buffer->info->family == CHIP_FIJI)) {
cmd_buffer->state.flush_bits |=
RADV_CMD_FLAG_VGT_STREAMOUT_SYNC;
}
@@ -4740,7 +4737,7 @@ radv_dispatch(struct radv_cmd_buffer *cmd_buffer,
{
struct radv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
bool has_prefetch =
- cmd_buffer->device->physical_device->rad_info.chip_class >=
GFX7;
+ cmd_buffer->info->chip_class >= GFX7;
bool pipeline_is_dirty = pipeline &&
pipeline !=
cmd_buffer->state.emitted_compute_pipeline;
@@ -5012,7 +5009,7 @@ void radv_initialize_dcc(struct radv_cmd_buffer
*cmd_buffer,
state->flush_bits |= radv_clear_dcc(cmd_buffer, image, range, value);
- if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX8) {
+ if (cmd_buffer->info->chip_class == GFX8) {
/* When DCC is enabled with mipmaps, some levels might not
* support fast clears and we have to initialize them as "fully
* expanded".
@@ -5390,7 +5387,7 @@ static void write_event(struct radv_cmd_buffer
*cmd_buffer,
} else {
/* Otherwise, sync all prior GPU work using an EOP event. */
si_cs_emit_write_event_eop(cs,
-
cmd_buffer->device->physical_device->rad_info.chip_class,
+ cmd_buffer->info->chip_class,
radv_cmd_buffer_uses_mec(cmd_buffer),
V_028A90_BOTTOM_OF_PIPE_TS, 0,
EOP_DATA_SEL_VALUE_32BIT, va, value,
@@ -5615,7 +5612,7 @@ static void radv_flush_vgt_streamout(struct
radv_cmd_buffer *cmd_buffer)
unsigned reg_strmout_cntl;
/* The register is at different places on different ASICs. */
- if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {
+ if (cmd_buffer->info->chip_class >= GFX7) {
reg_strmout_cntl = R_0300FC_CP_STRMOUT_CNTL;
radeon_set_uconfig_reg(cs, reg_strmout_cntl, 0);
} else {
@@ -5801,7 +5798,7 @@ void radv_CmdWriteBufferMarkerAMD(
radeon_emit(cs, va >> 32);
} else {
si_cs_emit_write_event_eop(cs,
-
cmd_buffer->device->physical_device->rad_info.chip_class,
+ cmd_buffer->info->chip_class,
radv_cmd_buffer_uses_mec(cmd_buffer),
V_028A90_BOTTOM_OF_PIPE_TS, 0,
EOP_DATA_SEL_VALUE_32BIT,
diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index 64042c7eb52..df3c1a7b722 100644
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -1174,6 +1174,7 @@ struct radv_cmd_buffer {
VK_LOADER_DATA _loader_data;
struct radv_device * device;
+ struct radeon_info *info;
struct radv_cmd_pool * pool;
struct list_head pool_link;
--
2.22.0
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