Hi all, I've been building Borg, a small open-source GPU (RV32I/RV64I CPU driving a custom FP16 shader processor, targeting both an ASIC via Tiny Tapeout and a Lattice ECP5 FPGA on the ULX3S board), and wrote a native Vulkan ICD for it in Mesa (src/borg/vulkan/) plus a small NIR-to-Borg-ISA compiler (src/borg/compiler/, Rust). Together they're about 5,000 lines.
A very early version of the chip has already been taped out (IHP SG13G2, via Tiny Tapeout), with further tapeouts planned. I presented a poster on it at HPG 2026 (https://www.highperformancegraphics.org/2026/schedule) alongside a demo: the unmodified Khronos vkcube sample — 12 triangles, 128x128 framebuffer, ~17fps — rendering on the real FPGA over a serial link. Vulkan conformance testing is very early: I started running VK-GL-CTS against it about two weeks ago and I'm at roughly 0.4% right now, mostly basic API-level cases. No illusions about where that stands. Separately, on a feature branch, the CPU booted OpenSBI + mainline Linux to an interactive shell last week — not merged yet, early groundwork for a future on-device driver. I have no concrete plans to upstream this at the moment — this is more of a "does this look reasonable" note than a submission. I do have some time and funding to keep working on it over the next few months, though, and would genuinely appreciate any feedback on the Vulkan driver and compiler code if anyone's willing to take a look. Full disclosure: I use Claude sometimes to help write this code — happy to discuss that, just please don't dismiss the feedback request on that basis alone. - Driver: https://github.com/gonsolo/mesa/tree/borg/src/borg/vulkan - Compiler: https://github.com/gonsolo/mesa/tree/borg/src/borg/compiler - Hardware/project: https://github.com/gonsolo/Borg I'm at SIGGRAPH this week if anyone wants to grab me for a chat in person. Thanks for reading, Andreas
