From: Alex Deucher <alexander.deuc...@amd.com>
Use per asic golden values.
Programming this register doesn't seem to be strictly
necessary on SI, but programming it wrong leads to
rendering issues or reduced performance so just
go ahead and program the golden values explicitly
to avoid any potential problems down the road.
Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
src/gallium/drivers/radeonsi/si_state.c | 11 +++++++++++
1 files changed, 11 insertions(+), 0 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_state.c
b/src/gallium/drivers/radeonsi/si_state.c
index db305d4..2bd55bb 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -2665,5 +2665,16 @@ void si_init_config(struct r600_context *rctx)
si_pm4_set_reg(pm4, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
+ switch (rctx->screen->family) {
+ case CHIP_TAHITI:
+ case CHIP_PITCAIRN:
+ si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x2a00126a);
+ break;
+ case CHIP_VERDE:
+ default:
+ si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x0000124a);
+ break;
+ }
+
si_pm4_set_state(rctx, init, pm4);
}
--
1.7.7.5
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