NOTE: This is a candidate for the Mesa stable branch.
---
src/gallium/drivers/r600/r600_llvm.c | 10 +++++++---
src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c | 17 +++++++++++++++++
src/gallium/winsys/radeon/drm/radeon_drm_winsys.c | 4 ++--
3 files changed, 26 insertions(+), 5 deletions(-)
diff --git a/src/gallium/drivers/r600/r600_llvm.c
b/src/gallium/drivers/r600/r600_llvm.c
index fa66fcc..e8b4679 100644
--- a/src/gallium/drivers/r600/r600_llvm.c
+++ b/src/gallium/drivers/r600/r600_llvm.c
@@ -18,7 +18,7 @@
#include <stdio.h>
-#if defined R600_USE_LLVM || defined HAVE_OPENCL
+//#if defined R600_USE_LLVM || defined HAVE_OPENCL
#define CONSTANT_BUFFER_0_ADDR_SPACE 9
#define CONSTANT_BUFFER_1_ADDR_SPACE (CONSTANT_BUFFER_0_ADDR_SPACE +
R600_UCP_CONST_BUFFER)
@@ -38,8 +38,12 @@ static LLVMValueRef llvm_fetch_const(
LLVMValueRef index =
LLVMBuildLoad(bld_base->base.gallivm->builder,
bld->addr[reg->Indirect.Index][reg->Indirect.SwizzleX], "");
offset[1] = LLVMBuildAdd(bld_base->base.gallivm->builder,
offset[1], index, "");
}
+ unsigned ConstantAddressSpace = CONSTANT_BUFFER_0_ADDR_SPACE ;
+ if (reg->Register.Dimension) {
+ ConstantAddressSpace += reg->Dimension.Index;
+ }
LLVMTypeRef const_ptr_type =
LLVMPointerType(LLVMArrayType(LLVMVectorType(bld_base->base.elem_type, 4),
1024),
-
CONSTANT_BUFFER_0_ADDR_SPACE);
+ ConstantAddressSpace);
LLVMValueRef const_ptr =
LLVMBuildIntToPtr(bld_base->base.gallivm->builder,
lp_build_const_int32(bld_base->base.gallivm, 0), const_ptr_type, "");
LLVMValueRef ptr = LLVMBuildGEP(bld_base->base.gallivm->builder,
const_ptr, offset, 2, "");
LLVMValueRef cvecval = LLVMBuildLoad(bld_base->base.gallivm->builder,
ptr, "");
@@ -602,4 +606,4 @@ unsigned r600_llvm_compile(
gpu_family, dump);
}
-#endif
+//#endif
diff --git a/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c
b/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c
index 0f90991..8902ae4 100644
--- a/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c
+++ b/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c
@@ -766,6 +766,22 @@ static void emit_icmp(
emit_data->output[emit_data->chan] = v;
}
+static void emit_ucmp(
+ const struct lp_build_tgsi_action * action,
+ struct lp_build_tgsi_context * bld_base,
+ struct lp_build_emit_data * emit_data)
+{
+ unsigned pred;
+ LLVMBuilderRef builder = bld_base->base.gallivm->builder;
+ LLVMContextRef context = bld_base->base.gallivm->context;
+
+
+ LLVMValueRef v = LLVMBuildFCmp(builder, LLVMRealUGE,
+ emit_data->args[0],
lp_build_const_float(bld_base->base.gallivm, 0.), "");
+
+ emit_data->output[emit_data->chan] = LLVMBuildSelect(builder, v,
emit_data->args[2], emit_data->args[1], "");
+}
+
static void emit_cmp(
const struct lp_build_tgsi_action *action,
struct lp_build_tgsi_context * bld_base,
@@ -1241,6 +1257,7 @@ void radeon_llvm_context_init(struct radeon_llvm_context
* ctx)
bld_base->op_actions[TGSI_OPCODE_USNE].emit = emit_icmp;
bld_base->op_actions[TGSI_OPCODE_U2F].emit = emit_u2f;
bld_base->op_actions[TGSI_OPCODE_XOR].emit = emit_xor;
+ bld_base->op_actions[TGSI_OPCODE_UCMP].emit = emit_ucmp;
bld_base->rsq_action.emit = build_tgsi_intrinsic_nomem;
bld_base->rsq_action.intr_name = "llvm.AMDGPU.rsq";
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
index 62ba4b1..bbfe664 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
@@ -372,7 +372,7 @@ static boolean do_winsys_init(struct radeon_drm_winsys *ws)
}
ws->info.r600_virtual_address = FALSE;
- if (ws->info.drm_minor >= 13) {
+/* if (ws->info.drm_minor >= 13) {
ws->info.r600_virtual_address = TRUE;
if (!radeon_get_drm_value(ws->fd, RADEON_INFO_VA_START, NULL,
&ws->info.r600_va_start))
@@ -380,7 +380,7 @@ static boolean do_winsys_init(struct radeon_drm_winsys *ws)
if (!radeon_get_drm_value(ws->fd, RADEON_INFO_IB_VM_MAX_SIZE, NULL,
&ws->info.r600_ib_vm_max_size))
ws->info.r600_virtual_address = FALSE;
- }
+ }*/
}
/* Get max pipes, this is only needed for compute shaders. All evergreen+
--
1.8.1.2
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