On Fri, Feb 22, 2013 at 05:02:12PM +0100, Michel Dänzer wrote:
> From: Michel Dänzer <michel.daen...@amd.com>
>
>
> Signed-off-by: Michel Dänzer <michel.daen...@amd.com>
> ---
> lib/Target/R600/SIInstrFormats.td | 24 ++++++++++++++++++++++++
> lib/Target/R600/SIInstrInfo.td | 22 ++++++++++++++++++++++
> lib/Target/R600/SIInstructions.td | 4 ++++
> 3 files changed, 50 insertions(+)
>
> diff --git a/lib/Target/R600/SIInstrFormats.td
> b/lib/Target/R600/SIInstrFormats.td
> index fe417d6..8f2a536 100644
> --- a/lib/Target/R600/SIInstrFormats.td
> +++ b/lib/Target/R600/SIInstrFormats.td
> @@ -281,6 +281,30 @@ class VINTRP <bits <2> op, dag outs, dag ins, string
> asm, list<dag> pattern> :
>
> let Uses = [EXEC] in {
>
> +class DS <bits<8> op, dag outs, dag ins, string asm, list<dag> pattern> :
> + Enc64 <outs, ins, asm, pattern> {
> +
> + bits<8> VDST;
> + bits<1> GDS;
> + bits<8> ADDR;
> + bits<8> DATA0;
> + bits<8> DATA1;
> + bits<8> OFFSET0;
> + bits<8> OFFSET1;
These field definitions should match the operand names in the
DS_{Load,Store}_Helper classes. Otherwise, the instruction
encoder will encode the fields based on the order they appear in the ins and
outs list, which can lead to subtle bugs.
> +
> + let Inst{7-0} = OFFSET0;
> + let Inst{15-8} = OFFSET1;
> + let Inst{17} = GDS;
> + let Inst{25-18} = op;
> + let Inst{31-26} = 0x36; //encoding
> + let Inst{39-32} = ADDR;
> + let Inst{47-40} = DATA0;
> + let Inst{55-48} = DATA1;
> + let Inst{63-56} = VDST;
> +
> + let LGKM_CNT = 1;
> +}
> +
> class MUBUF <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
> Enc64<outs, ins, asm, pattern> {
>
> diff --git a/lib/Target/R600/SIInstrInfo.td b/lib/Target/R600/SIInstrInfo.td
> index 99168ce..1d8ab5e 100644
> --- a/lib/Target/R600/SIInstrInfo.td
> +++ b/lib/Target/R600/SIInstrInfo.td
> @@ -244,6 +244,28 @@ class VOP3_64 <bits<9> op, string opName, list<dag>
> pattern> : VOP3 <
> // Vector I/O classes
>
> //===----------------------------------------------------------------------===//
>
> +class DS_Load_Helper <bits<8> op, string asm, RegisterClass regClass> : DS <
> + op,
> + (outs regClass:$dst),
This should be renamed to $vdst to match the field name.
> + (ins i1imm:$gds, VReg_32:$addr, VReg_32:$data0, VReg_32:$data1,
> + i8imm:$offset0, i8imm:$offset1),
> + asm#" $dst, $gds, $addr, $data0, $data1, $offset0, $offset1, [M0]",
> + []> {
> + let mayLoad = 1;
> + let mayStore = 0;
> +}
> +
> +class DS_Store_Helper <bits<8> op, string asm, RegisterClass regClass> : DS <
> + op,
> + (outs),
> + (ins regClass:$vdata, i1imm:$gds, VReg_32:$addr, VReg_32:$data0,
> VReg_32:$data1,
$vdata => $vdst
> + i8imm:$offset0, i8imm:$offset1),
> + asm#" $gds, $addr, $data0, $data1, $offset0, $offset1, [M0]",
> + []> {
> + let mayStore = 1;
> + let mayLoad = 0;
> +}
> +
> class MTBUF_Store_Helper <bits<3> op, string asm, RegisterClass regClass> :
> MTBUF <
> op,
> (outs),
> diff --git a/lib/Target/R600/SIInstructions.td
> b/lib/Target/R600/SIInstructions.td
> index 99ec6eb..7152c49 100644
> --- a/lib/Target/R600/SIInstructions.td
> +++ b/lib/Target/R600/SIInstructions.td
> @@ -355,6 +355,10 @@ defm V_CMP_CLASS_F32 : VOPC_32 <0x00000088,
> "V_CMP_CLASS_F32">;
> defm V_CMPX_CLASS_F32 : VOPC_32 <0x00000098, "V_CMPX_CLASS_F32">;
> defm V_CMP_CLASS_F64 : VOPC_64 <0x000000a8, "V_CMP_CLASS_F64">;
> defm V_CMPX_CLASS_F64 : VOPC_64 <0x000000b8, "V_CMPX_CLASS_F64">;
> +
> +def DS_WRITE_B32 : DS_Store_Helper <0x0000000d, "DS_WRITE_B32", VReg_32>;
> +def DS_READ_B32 : DS_Load_Helper <0x00000036, "DS_READ_B32", VReg_32>;
> +
> //def BUFFER_LOAD_FORMAT_X : MUBUF_ <0x00000000, "BUFFER_LOAD_FORMAT_X", []>;
> //def BUFFER_LOAD_FORMAT_XY : MUBUF_ <0x00000001, "BUFFER_LOAD_FORMAT_XY",
> []>;
> //def BUFFER_LOAD_FORMAT_XYZ : MUBUF_ <0x00000002, "BUFFER_LOAD_FORMAT_XYZ",
> []>;
> --
> 1.8.1.3
>
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