Am 03.04.2013 15:19, schrieb Michel Dänzer:
On Mit, 2013-03-27 at 17:57 +0100, Christian König wrote:
the attached patches dynamically adjust the writemask of MIMG
instructions depending on the used components. Additional to that it
also adjust the register class of MIMG instruction so that we also
reduce register pressure.
There's mainly one thing that isn't clear to me: My understanding from
the ISA is that even if the instruction writemask operand has 'gaps',
e.g. 0x9, the enabled components will always be written to consecutive
VGPRs. So in this example, the instruction would write to two
consecutive VGPRs, one for component 0/'x' and one for component 3/'w'
of a four component vector. Is this handled correctly?
Yes your understanding is correct, and it is indeed handled correctly.
I just analyze the used register components to figure out the needed
writemask and while doing so remember which instruction uses which
component. So after updating the writemask I just change the index of
the used component as well.
Christian.
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