Sounds definitely an improvement.
Long term I think the cache is probably not worth to keep any texture cache at
all.
Jose
----- Original Message -----
> From: Roland Scheidegger <srol...@vmware.com>
>
> Initially we had NUM_TEX_TILE_ENTRIES of 50, however this was using too much
> memory (mostly because the tile cache is operating on fixed max current
> sampler views which could be fixed but that's another topic). So it was
> decreased to 4. However this is a ridiculously low number which can't
> actually really work (the number of tiles needed for as little as
> a single quad with linear_mipmap_linear is 2 to 8 for a 2d texture, and
> 4 to 16 for a 3d texture), as it just about guarantees there will be
> cache thrashing sometimes (just about always for 3d textures in fact, since
> while there are 4 entries the cache is direct mapped).
> So increase that number to 16 (which is still on the low side for direct
> mapped cache though I guess using something like 4-way associativity would
> be more effective than increasing this further) which has at least some good
> chance to avoid thrashing. Since we don't want to increase memory
> requirements
> however in turn decrease the tile size accordingly from 64 to 32 (as a bonus
> point this also decreases the cost of texture thrashing which might still
> happen sometimes).
> I've seen performance improvement in the order of factor ~200 (specifically,
> drawing the first frame from the replay from bug 41787 needs "only" ~10s
> instead of ~30min, meaning I can actually compare the output with other
> drivers...) with this.
> ---
> src/gallium/drivers/softpipe/sp_tex_tile_cache.h | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/src/gallium/drivers/softpipe/sp_tex_tile_cache.h
> b/src/gallium/drivers/softpipe/sp_tex_tile_cache.h
> index 0ea82b3..2fd6f12 100644
> --- a/src/gallium/drivers/softpipe/sp_tex_tile_cache.h
> +++ b/src/gallium/drivers/softpipe/sp_tex_tile_cache.h
> @@ -40,7 +40,7 @@ struct softpipe_tex_tile_cache;
> /**
> * Cache tile size (width and height). This needs to be a power of two.
> */
> -#define TEX_TILE_SIZE_LOG2 6
> +#define TEX_TILE_SIZE_LOG2 5
> #define TEX_TILE_SIZE (1 << TEX_TILE_SIZE_LOG2)
>
>
> @@ -73,7 +73,7 @@ struct softpipe_tex_cached_tile
> } data;
> };
>
> -#define NUM_TEX_TILE_ENTRIES 4
> +#define NUM_TEX_TILE_ENTRIES 16
>
> struct softpipe_tex_tile_cache
> {
> --
> 1.7.9.5
>
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