For HSW GT3 clear rectangle must be aligned to two times the number of pixels in the table shown in Ivy Bridge PRM, Vol2 Part1 11.7. It should be safe to do this for all gen7 systems unless we see any performance regressions. I observed no piglit, gles3conform regressions with this patch.
It fixes: https://bugs.freedesktop.org/show_bug.cgi?id=65744 Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com> --- Thanks Paul for your great help in figuring out the fix. src/mesa/drivers/dri/i965/brw_blorp_clear.cpp | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp b/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp index bf11135..2bebe8e 100644 --- a/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp +++ b/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp @@ -261,10 +261,14 @@ brw_blorp_clear_params::brw_blorp_clear_params(struct brw_context *brw, intel_get_non_msrt_mcs_alignment(intel, irb->mt, &x_align, &y_align); x_align *= 16; y_align *= 32; - x0 = ROUND_DOWN_TO(x0, x_align); - y0 = ROUND_DOWN_TO(y0, y_align); - x1 = ALIGN(x1, x_align); - y1 = ALIGN(y1, y_align); + /* For HSW GT3 clear rectangle must be aligned to two times the number + * of pixels in the table. + */ + + x0 = ROUND_DOWN_TO(x0, (intel->gen > 6 ? 2 * x_align : x_align)); + y0 = ROUND_DOWN_TO(y0, (intel->gen > 6 ? 2 * y_align : y_align)); + x1 = ALIGN(x1, (intel->gen > 6 ? 2 * x_align : x_align)); + y1 = ALIGN(y1, (intel->gen > 6 ? 2 * y_align : y_align)); /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render * Target(s)", beneath the "Fast Color Clear" bullet (p327): -- 1.8.1.4 _______________________________________________ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev