The value that's split into width/height/depth needs to be the size of the buffer minus one. This makes it consistent with the constant buffer and shader time SURFACE_STATE setup code.
Signed-off-by: Kenneth Graunke <[email protected]> Cc: Paul Berry <[email protected]> Cc: Eric Anholt <[email protected]> --- src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 2 +- src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c index 8d87786..0078161 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c +++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c @@ -228,7 +228,7 @@ brw_update_buffer_texture_surface(struct gl_context *ctx, *surf_offset + 4, bo, 0, I915_GEM_DOMAIN_SAMPLER, 0); - int w = intel_obj->Base.Size / texel_size; + int w = (intel_obj->Base.Size / texel_size) - 1; surf[2] = ((w & 0x7f) << BRW_SURFACE_WIDTH_SHIFT | ((w >> 7) & 0x1fff) << BRW_SURFACE_HEIGHT_SHIFT); surf[3] = (((w >> 20) & 0x7f) << BRW_SURFACE_DEPTH_SHIFT | diff --git a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c index 37e3174..c38843f 100644 --- a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c +++ b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c @@ -260,7 +260,7 @@ gen7_update_buffer_texture_surface(struct gl_context *ctx, I915_GEM_DOMAIN_SAMPLER, 0); int texel_size = _mesa_get_format_bytes(format); - int w = intel_obj->Base.Size / texel_size; + int w = (intel_obj->Base.Size / texel_size) - 1; /* note that these differ from GEN6 */ surf[2] = SET_FIELD(w & 0x7f, GEN7_SURFACE_WIDTH) | /* bits 6:0 of size */ -- 1.8.3.4 _______________________________________________ mesa-dev mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/mesa-dev
