While working on patch b4c3b83 (i965: Fix vertical alignment for multisampled buffers) I noticed that we were failing to follow another alignment rule: on gen7, render targets using Y tiling must have a vertical alignment of 4. This patch series ensures that we follow that rule by preferring a vertical alignment of 4 the hardware allows it (patch 1), and disallowing Y tiling of renderable surfaces when the hardware doesn't allow an alignment of 4 (patch 2).
I'm not aware of any hardware misbehaviour resulting from our previous failure to follow this alignment rule, so I'm going to recommend that these patches *not* be backported to stable branches. [PATCH 1/2] i965/gen7: Prefer vertical alignment of 4 when possible. [PATCH 2/2] i965/gen7: Disallow Y tiling of renderable surfaces with valign of 2. _______________________________________________ mesa-dev mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/mesa-dev
