Francisco Jerez <curroje...@riseup.net> writes: > Petri Latvala <petri.latv...@intel.com> writes: >[...] >> Not saying it kosher either way though, calling assignment operator in a >> constructor is iffy :P. The proper way is selecting the correct base >> class constructor to call. >> Again, that probably belongs to a separate clean-up commit... See attachment.
>> >> -- >> Petri Latvala >> >> _______________________________________________ >> mesa-dev mailing list >> mesa-dev@lists.freedesktop.org >> http://lists.freedesktop.org/mailman/listinfo/mesa-dev
From e1660cb525ced30db38dd2e373da7bf62235c132 Mon Sep 17 00:00:00 2001
From: Francisco Jerez <curroje...@riseup.net>
Date: Tue, 3 Dec 2013 09:53:31 -0800
Subject: [PATCH] i965: Delegate common register initialization to the
backend_reg constructors.
And stop bashing the register structure with zeroes on ::init().
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 58 +++++++------------
src/mesa/drivers/dri/i965/brw_fs.h | 5 +-
src/mesa/drivers/dri/i965/brw_shader.cpp | 38 +++++++++++-
src/mesa/drivers/dri/i965/brw_shader.h | 4 ++
src/mesa/drivers/dri/i965/brw_vec4.cpp | 80 ++++++++++----------------
src/mesa/drivers/dri/i965/brw_vec4.h | 10 ++--
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 20 +++----
7 files changed, 107 insertions(+), 108 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp
index ca152d1..f5d85ad 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -378,57 +378,51 @@ fs_visitor::can_do_source_mods(fs_inst *inst)
void
fs_reg::init()
{
- memset(this, 0, sizeof(*this));
+ negate = false;
+ abs = false;
+ subreg_offset = 0;
stride = 1;
+ reladdr = NULL;
}
/** Generic unset register constructor. */
fs_reg::fs_reg()
{
init();
- this->file = BAD_FILE;
}
/** Immediate value constructor. */
-fs_reg::fs_reg(float f)
+fs_reg::fs_reg(float f) :
+ backend_reg(f)
{
init();
- this->file = IMM;
- this->type = BRW_REGISTER_TYPE_F;
- this->imm.f = f;
}
/** Immediate value constructor. */
-fs_reg::fs_reg(int32_t i)
+fs_reg::fs_reg(int32_t i) :
+ backend_reg(i)
{
init();
- this->file = IMM;
- this->type = BRW_REGISTER_TYPE_D;
- this->imm.i = i;
}
/** Immediate value constructor. */
-fs_reg::fs_reg(uint32_t u)
+fs_reg::fs_reg(uint32_t u) :
+ backend_reg(u)
{
init();
- this->file = IMM;
- this->type = BRW_REGISTER_TYPE_UD;
- this->imm.u = u;
}
/** Fixed brw_reg. */
-fs_reg::fs_reg(struct brw_reg fixed_hw_reg)
+fs_reg::fs_reg(struct brw_reg fixed_hw_reg) :
+ backend_reg(fixed_hw_reg)
{
init();
- this->file = HW_REG;
- this->fixed_hw_reg = fixed_hw_reg;
- this->type = fixed_hw_reg.type;
}
-fs_reg::fs_reg(const backend_reg ®)
+fs_reg::fs_reg(const backend_reg ®) :
+ backend_reg(reg)
{
init();
- *static_cast<backend_reg *>(this) = reg;
}
bool
@@ -811,33 +805,23 @@ fs_visitor::virtual_grf_alloc(int size)
return virtual_grf_count++;
}
-/** Fixed HW reg constructor. */
-fs_reg::fs_reg(enum register_file file, int reg)
+fs_reg::fs_reg(enum register_file file, int reg) :
+ backend_reg(file, reg, BRW_REGISTER_TYPE_F)
{
init();
- this->file = file;
- this->reg = reg;
- this->type = BRW_REGISTER_TYPE_F;
}
-/** Fixed HW reg constructor. */
-fs_reg::fs_reg(enum register_file file, int reg, uint32_t type)
+fs_reg::fs_reg(enum register_file file, int reg, uint32_t type) :
+ backend_reg(file, reg, type)
{
init();
- this->file = file;
- this->reg = reg;
- this->type = type;
}
-/** Automatic reg constructor. */
-fs_reg::fs_reg(class fs_visitor *v, const struct glsl_type *type)
+fs_reg::fs_reg(class fs_visitor *v, const struct glsl_type *type) :
+ backend_reg(GRF, v->virtual_grf_alloc(v->type_size(type)),
+ brw_type_for_base_type(type))
{
init();
-
- this->file = GRF;
- this->reg = v->virtual_grf_alloc(v->type_size(type));
- this->reg_offset = 0;
- this->type = brw_type_for_base_type(type);
}
fs_reg *
diff --git a/src/mesa/drivers/dri/i965/brw_fs.h b/src/mesa/drivers/dri/i965/brw_fs.h
index ae4a6f5..7a9b727 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.h
+++ b/src/mesa/drivers/dri/i965/brw_fs.h
@@ -63,8 +63,6 @@ class fs_reg : public backend_reg {
public:
DECLARE_RALLOC_CXX_OPERATORS(fs_reg)
- void init();
-
fs_reg();
fs_reg(float f);
fs_reg(int32_t i);
@@ -90,6 +88,9 @@ public:
int stride; /**< Register region horizontal stride */
fs_reg *reladdr;
+
+private:
+ void init();
};
static inline fs_reg
diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp b/src/mesa/drivers/dri/i965/brw_shader.cpp
index d903bb5..7667c50 100644
--- a/src/mesa/drivers/dri/i965/brw_shader.cpp
+++ b/src/mesa/drivers/dri/i965/brw_shader.cpp
@@ -571,12 +571,48 @@ backend_reg::backend_reg() :
backend_reg::backend_reg(struct brw_reg fixed_hw_reg) :
file(HW_REG),
reg(0), reg_offset(0),
- type(BRW_REGISTER_TYPE_UD),
+ type(fixed_hw_reg.type),
fixed_hw_reg(fixed_hw_reg),
imm()
{
}
+backend_reg::backend_reg(float f) :
+ file(IMM),
+ reg(0), reg_offset(0),
+ type(BRW_REGISTER_TYPE_F),
+ fixed_hw_reg()
+{
+ imm.f = f;
+}
+
+backend_reg::backend_reg(int32_t i) :
+ file(IMM),
+ reg(0), reg_offset(0),
+ type(BRW_REGISTER_TYPE_D),
+ fixed_hw_reg()
+{
+ imm.i = i;
+}
+
+backend_reg::backend_reg(uint32_t u) :
+ file(IMM),
+ reg(0), reg_offset(0),
+ type(BRW_REGISTER_TYPE_UD),
+ fixed_hw_reg()
+{
+ imm.u = u;
+}
+
+backend_reg::backend_reg(enum register_file file, int reg, uint32_t type) :
+ file(file),
+ reg(reg), reg_offset(0),
+ type(type),
+ fixed_hw_reg(),
+ imm()
+{
+}
+
bool
backend_reg::is_zero() const
{
diff --git a/src/mesa/drivers/dri/i965/brw_shader.h b/src/mesa/drivers/dri/i965/brw_shader.h
index 90b8157..72f5e8a 100644
--- a/src/mesa/drivers/dri/i965/brw_shader.h
+++ b/src/mesa/drivers/dri/i965/brw_shader.h
@@ -44,6 +44,10 @@ class backend_reg {
public:
backend_reg();
backend_reg(struct brw_reg reg);
+ backend_reg(float f);
+ backend_reg(int32_t i);
+ backend_reg(uint32_t u);
+ backend_reg(enum register_file file, int reg, uint32_t type);
bool is_zero() const;
bool is_one() const;
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp b/src/mesa/drivers/dri/i965/brw_vec4.cpp
index e98fff5..08729d3 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4.cpp
@@ -62,17 +62,17 @@ swizzle_for_size(int size)
void
src_reg::init()
{
- memset(this, 0, sizeof(*this));
-
- this->file = BAD_FILE;
+ swizzle = BRW_SWIZZLE_XXXX;
+ negate = false;
+ abs = false;
+ reladdr = NULL;
}
-src_reg::src_reg(register_file file, int reg, const glsl_type *type)
+src_reg::src_reg(register_file file, int reg, const glsl_type *type) :
+ backend_reg(file, reg, BRW_REGISTER_TYPE_UD)
{
init();
- this->file = file;
- this->reg = reg;
if (type && (type->is_scalar() || type->is_vector() || type->is_matrix()))
this->swizzle = swizzle_for_size(type->vector_elements);
else
@@ -85,57 +85,44 @@ src_reg::src_reg()
init();
}
-src_reg::src_reg(float f)
+src_reg::src_reg(float f) :
+ backend_reg(f)
{
init();
-
- this->file = IMM;
- this->type = BRW_REGISTER_TYPE_F;
- this->imm.f = f;
}
-src_reg::src_reg(uint32_t u)
+src_reg::src_reg(uint32_t u) :
+ backend_reg(u)
{
init();
-
- this->file = IMM;
- this->type = BRW_REGISTER_TYPE_UD;
- this->imm.u = u;
}
-src_reg::src_reg(int32_t i)
+src_reg::src_reg(int32_t i) :
+ backend_reg(i)
{
init();
-
- this->file = IMM;
- this->type = BRW_REGISTER_TYPE_D;
- this->imm.i = i;
}
-src_reg::src_reg(struct brw_reg reg)
+src_reg::src_reg(struct brw_reg reg) :
+ backend_reg(reg)
{
init();
-
- this->file = HW_REG;
- this->fixed_hw_reg = reg;
- this->type = reg.type;
}
-src_reg::src_reg(const backend_reg ®)
+src_reg::src_reg(const backend_reg ®) :
+ backend_reg(reg)
{
init();
- *static_cast<backend_reg *>(this) = reg;
- this->swizzle = BRW_SWIZZLE_XYZW;
}
-src_reg::src_reg(dst_reg reg)
+src_reg::src_reg(dst_reg reg) :
+ backend_reg(reg)
{
int swizzles[4];
int next_chan = 0;
int last = 0;
init();
- *static_cast<backend_reg *>(this) = reg;
this->reladdr = reg.reladdr;
for (int i = 0; i < 4; i++) {
@@ -156,9 +143,8 @@ src_reg::src_reg(dst_reg reg)
void
dst_reg::init()
{
- memset(this, 0, sizeof(*this));
- this->file = BAD_FILE;
this->writemask = WRITEMASK_XYZW;
+ this->reladdr = NULL;
}
dst_reg::dst_reg()
@@ -166,44 +152,36 @@ dst_reg::dst_reg()
init();
}
-dst_reg::dst_reg(register_file file, int reg)
+dst_reg::dst_reg(register_file file, int reg) :
+ backend_reg(file, reg, BRW_REGISTER_TYPE_UD)
{
init();
-
- this->file = file;
- this->reg = reg;
}
dst_reg::dst_reg(register_file file, int reg, const glsl_type *type,
- int writemask)
+ int writemask) :
+ backend_reg(file, reg, brw_type_for_base_type(type))
{
init();
-
- this->file = file;
- this->reg = reg;
- this->type = brw_type_for_base_type(type);
this->writemask = writemask;
}
-dst_reg::dst_reg(struct brw_reg reg)
+dst_reg::dst_reg(struct brw_reg reg) :
+ backend_reg(reg)
{
init();
-
- this->file = HW_REG;
- this->fixed_hw_reg = reg;
- this->type = reg.type;
}
-dst_reg::dst_reg(const backend_reg ®)
+dst_reg::dst_reg(const backend_reg ®) :
+ backend_reg(reg)
{
init();
- *static_cast<backend_reg *>(this) = reg;
}
-dst_reg::dst_reg(src_reg reg)
+dst_reg::dst_reg(src_reg reg) :
+ backend_reg(reg)
{
init();
- *static_cast<backend_reg *>(this) = reg;
this->reladdr = reg.reladdr;
/* How should we do writemasking when converting from a src_reg? It seems
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.h b/src/mesa/drivers/dri/i965/brw_vec4.h
index 341bdbb..80b91c1 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.h
+++ b/src/mesa/drivers/dri/i965/brw_vec4.h
@@ -94,8 +94,6 @@ class src_reg : public backend_reg
public:
DECLARE_RALLOC_CXX_OPERATORS(src_reg)
- void init();
-
src_reg(register_file file, int reg, const glsl_type *type);
src_reg();
src_reg(float f);
@@ -115,6 +113,9 @@ public:
bool abs;
src_reg *reladdr;
+
+private:
+ void init();
};
static inline src_reg
@@ -161,8 +162,6 @@ class dst_reg : public backend_reg
public:
DECLARE_RALLOC_CXX_OPERATORS(dst_reg)
- void init();
-
dst_reg();
dst_reg(register_file file, int reg);
dst_reg(register_file file, int reg, const glsl_type *type, int writemask);
@@ -175,6 +174,9 @@ public:
int writemask; /**< Bitfield of WRITEMASK_[XYZW] */
src_reg *reladdr;
+
+private:
+ void init();
};
static inline dst_reg
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
index e04fc69..5c90880 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
@@ -602,36 +602,30 @@ vec4_visitor::virtual_grf_alloc(int size)
return virtual_grf_count++;
}
-src_reg::src_reg(class vec4_visitor *v, const struct glsl_type *type)
+src_reg::src_reg(class vec4_visitor *v, const struct glsl_type *type) :
+ backend_reg(GRF, v->virtual_grf_alloc(type_size(type)),
+ brw_type_for_base_type(type))
{
init();
- this->file = GRF;
- this->reg = v->virtual_grf_alloc(type_size(type));
-
if (type->is_array() || type->is_record()) {
this->swizzle = BRW_SWIZZLE_NOOP;
} else {
this->swizzle = swizzle_for_size(type->vector_elements);
}
-
- this->type = brw_type_for_base_type(type);
}
-dst_reg::dst_reg(class vec4_visitor *v, const struct glsl_type *type)
+dst_reg::dst_reg(class vec4_visitor *v, const struct glsl_type *type) :
+ backend_reg(GRF, v->virtual_grf_alloc(type_size(type)),
+ brw_type_for_base_type(type))
{
init();
- this->file = GRF;
- this->reg = v->virtual_grf_alloc(type_size(type));
-
if (type->is_array() || type->is_record()) {
this->writemask = WRITEMASK_XYZW;
} else {
this->writemask = (1 << type->vector_elements) - 1;
}
-
- this->type = brw_type_for_base_type(type);
}
void
@@ -983,7 +977,7 @@ vec4_visitor::visit(ir_variable *ir)
return;
} else if (ir->type->contains_atomic()) {
- reg = new(this->mem_ctx) dst_reg(ir->atomic.offset);
+ reg = new(this->mem_ctx) dst_reg(src_reg(ir->atomic.offset));
brw_mark_surface_used(stage_prog_data,
stage_prog_data->binding_table.abo_start +
--
1.8.4
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