We intended to set these 64-bit addresses to 0, and set the enable bit. But, I accidentally placed the DWord with the high bits first, when it should have been second.
This generally worked out, by luck - presumably General State Base Address is initially zero, and ends up remaining that way in our contexts since we bungled the "modify enable" bit. Signed-off-by: Kenneth Graunke <[email protected]> --- src/mesa/drivers/dri/i965/gen8_misc_state.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/i965/gen8_misc_state.c b/src/mesa/drivers/dri/i965/gen8_misc_state.c index 4641388..d26674e 100644 --- a/src/mesa/drivers/dri/i965/gen8_misc_state.c +++ b/src/mesa/drivers/dri/i965/gen8_misc_state.c @@ -36,8 +36,8 @@ static void upload_state_base_address(struct brw_context *brw) BEGIN_BATCH(16); OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (16 - 2)); /* General state base address: stateless DP read/write requests */ - OUT_BATCH(0); OUT_BATCH(BDW_MOCS_WB << 2 | 1); + OUT_BATCH(0); OUT_BATCH(BDW_MOCS_WB << 16); /* Surface state base address: */ OUT_RELOC64(brw->batch.bo, I915_GEM_DOMAIN_SAMPLER, 0, @@ -47,8 +47,8 @@ static void upload_state_base_address(struct brw_context *brw) I915_GEM_DOMAIN_RENDER | I915_GEM_DOMAIN_INSTRUCTION, 0, BDW_MOCS_WB << 4 | 1); /* Indirect object base address: MEDIA_OBJECT data */ - OUT_BATCH(0); OUT_BATCH(BDW_MOCS_WB << 4 | 1); + OUT_BATCH(0); /* Instruction base address: shader kernels (incl. SIP) */ OUT_RELOC64(brw->cache.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BDW_MOCS_WB << 4 | 1); -- 1.9.2 _______________________________________________ mesa-dev mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/mesa-dev
