Due to the destination register width of 1 or 2, these instructions get ExecSize 1 or 2. But dir and offset (used as src0) are both registers of width 4, violating the execsize >= width assertion.
I honestly don't think this could have ever worked. Fixes Piglit's polygon-offset and polygon-mode-offset tests on Gen4-5. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=70441 Signed-off-by: Kenneth Graunke <kenn...@whitecape.org> --- src/mesa/drivers/dri/i965/brw_clip_unfilled.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) Only tested on Ironlake. No Piglit regressions. Two fixes. diff --git a/src/mesa/drivers/dri/i965/brw_clip_unfilled.c b/src/mesa/drivers/dri/i965/brw_clip_unfilled.c index 5104276..82d7b64 100644 --- a/src/mesa/drivers/dri/i965/brw_clip_unfilled.c +++ b/src/mesa/drivers/dri/i965/brw_clip_unfilled.c @@ -198,7 +198,7 @@ static void compute_offset( struct brw_clip_compile *c ) struct brw_reg dir = c->reg.dir; brw_math_invert(p, get_element(off, 2), get_element(dir, 2)); - brw_MUL(p, vec2(off), dir, get_element(off, 2)); + brw_MUL(p, vec2(off), vec2(dir), get_element(off, 2)); brw_CMP(p, vec1(brw_null_reg()), @@ -210,8 +210,8 @@ static void compute_offset( struct brw_clip_compile *c ) brw_abs(get_element(off, 0)), brw_abs(get_element(off, 1))); brw_inst_set_pred_control(brw, brw_last_inst, BRW_PREDICATE_NORMAL); - brw_MUL(p, vec1(off), off, brw_imm_f(c->key.offset_factor)); - brw_ADD(p, vec1(off), off, brw_imm_f(c->key.offset_units)); + brw_MUL(p, vec1(off), vec1(off), brw_imm_f(c->key.offset_factor)); + brw_ADD(p, vec1(off), vec1(off), brw_imm_f(c->key.offset_units)); } -- 1.9.2 _______________________________________________ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
