These too are
Reviewed-by: Jason Ekstrand <jason.ekstr...@intel.com>
On Wed, Nov 12, 2014 at 11:28 AM, Matt Turner <matts...@gmail.com> wrote:
> texture_offset was only used by some texturing operations, and offset
> was only used by spill/unspill and some URB operations. These fields are
> never used at the same time.
> ---
> src/mesa/drivers/dri/i965/brw_fs_cse.cpp | 2 +-
> src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 6 +++---
> src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 4 ++--
> src/mesa/drivers/dri/i965/brw_shader.h | 3 +--
> src/mesa/drivers/dri/i965/brw_vec4_generator.cpp | 6 +++---
> src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 7 +++----
> 6 files changed, 13 insertions(+), 15 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_fs_cse.cpp
> b/src/mesa/drivers/dri/i965/brw_fs_cse.cpp
> index 5fdbf46..b1c433e 100644
> --- a/src/mesa/drivers/dri/i965/brw_fs_cse.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_fs_cse.cpp
> @@ -157,7 +157,7 @@ instructions_match(fs_inst *a, fs_inst *b)
> a->conditional_mod == b->conditional_mod &&
> a->dst.type == b->dst.type &&
> a->sources == b->sources &&
> - (a->is_tex() ? (a->texture_offset == b->texture_offset &&
> + (a->is_tex() ? (a->offset == b->offset &&
> a->mlen == b->mlen &&
> a->regs_written == b->regs_written &&
> a->base_mrf == b->base_mrf &&
> diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
> b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
> index c95beb6..dc9e803 100644
> --- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
> @@ -556,7 +556,7 @@ fs_generator::generate_tex(fs_inst *inst, struct
> brw_reg dst, struct brw_reg src
> * Otherwise, we can use an implied move from g0 to the first message
> reg.
> */
> if (inst->header_present) {
> - if (brw->gen < 6 && !inst->texture_offset) {
> + if (brw->gen < 6 && !inst->offset) {
> /* Set up an implied move from g0 to the MRF. */
> src = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW);
> } else {
> @@ -575,10 +575,10 @@ fs_generator::generate_tex(fs_inst *inst, struct
> brw_reg dst, struct brw_reg src
> /* Explicitly set up the message header by copying g0 to the
> MRF. */
> brw_MOV(p, header_reg, brw_vec8_grf(0, 0));
>
> - if (inst->texture_offset) {
> + if (inst->offset) {
> /* Set the offset bits in DWord 2. */
> brw_MOV(p, get_element_ud(header_reg, 2),
> - brw_imm_ud(inst->texture_offset));
> + brw_imm_ud(inst->offset));
> }
>
> brw_adjust_sampler_state_pointer(p, header_reg, sampler_index,
> dst);
> diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
> b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
> index 4e1badd..21334a2 100644
> --- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
> @@ -1918,10 +1918,10 @@ fs_visitor::emit_texture(ir_texture_opcode op,
> inst->shadow_compare = true;
>
> if (offset_value.file == IMM)
> - inst->texture_offset = offset_value.fixed_hw_reg.dw1.ud;
> + inst->offset = offset_value.fixed_hw_reg.dw1.ud;
>
> if (op == ir_tg4) {
> - inst->texture_offset |=
> + inst->offset |=
> gather_channel(gather_component, sampler) << 16; /* M0.2:16-17 */
>
> if (brw->gen == 6)
> diff --git a/src/mesa/drivers/dri/i965/brw_shader.h
> b/src/mesa/drivers/dri/i965/brw_shader.h
> index 94db987..32460e2 100644
> --- a/src/mesa/drivers/dri/i965/brw_shader.h
> +++ b/src/mesa/drivers/dri/i965/brw_shader.h
> @@ -112,8 +112,7 @@ struct backend_instruction {
> const char *annotation;
> /** @} */
>
> - uint32_t texture_offset; /**< Texture offset bitfield */
> - uint32_t offset; /**< spill/unspill offset */
> + uint32_t offset; /**< spill/unspill offset or texture offset bitfield
> */
> uint8_t mlen; /**< SEND message length */
> int8_t base_mrf; /**< First MRF in the SEND message, if mlen is
> nonzero. */
> uint8_t target; /**< MRT target. */
> diff --git a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
> b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
> index e522567..0776a91 100644
> --- a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
> @@ -319,7 +319,7 @@ vec4_generator::generate_tex(vec4_instruction *inst,
> * use an implied move from g0 to the first message register.
> */
> if (inst->header_present) {
> - if (brw->gen < 6 && !inst->texture_offset) {
> + if (brw->gen < 6 && !inst->offset) {
> /* Set up an implied move from g0 to the MRF. */
> src = brw_vec8_grf(0, 0);
> } else {
> @@ -333,10 +333,10 @@ vec4_generator::generate_tex(vec4_instruction *inst,
>
> brw_set_default_access_mode(p, BRW_ALIGN_1);
>
> - if (inst->texture_offset) {
> + if (inst->offset) {
> /* Set the texel offset bits in DWord 2. */
> brw_MOV(p, get_element_ud(header, 2),
> - brw_imm_ud(inst->texture_offset));
> + brw_imm_ud(inst->offset));
> }
>
> brw_adjust_sampler_state_pointer(p, header, sampler_index, dst);
> diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
> b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
> index b46879b..f08b9a9 100644
> --- a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
> @@ -46,7 +46,6 @@ vec4_instruction::vec4_instruction(vec4_visitor *v,
> this->no_dd_check = false;
> this->writes_accumulator = false;
> this->conditional_mod = BRW_CONDITIONAL_NONE;
> - this->texture_offset = 0;
> this->target = 0;
> this->shadow_compare = false;
> this->ir = v->base_ir;
> @@ -2550,14 +2549,14 @@ vec4_visitor::visit(ir_texture *ir)
> vec4_instruction *inst = new(mem_ctx) vec4_instruction(this, opcode);
>
> if (ir->offset != NULL && !has_nonconstant_offset) {
> - inst->texture_offset =
> + inst->offset =
> brw_texture_offset(ctx, ir->offset->as_constant()->value.i,
> ir->offset->type->vector_elements);
> }
>
> /* Stuff the channel select bits in the top of the texture offset */
> if (ir->op == ir_tg4)
> - inst->texture_offset |= gather_channel(ir, sampler) << 16;
> + inst->offset |= gather_channel(ir, sampler) << 16;
>
> /* The message header is necessary for:
> * - Gen4 (always)
> @@ -2566,7 +2565,7 @@ vec4_visitor::visit(ir_texture *ir)
> * - Sampler indices too large to fit in a 4-bit value.
> */
> inst->header_present =
> - brw->gen < 5 || inst->texture_offset != 0 || ir->op == ir_tg4 ||
> + brw->gen < 5 || inst->offset != 0 || ir->op == ir_tg4 ||
> is_high_sampler(brw, sampler_reg);
> inst->base_mrf = 2;
> inst->mlen = inst->header_present + 1; /* always at least one */
> --
> 2.0.4
>
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> mesa-dev mailing list
> mesa-dev@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/mesa-dev
>
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