On Wed, Mar 4, 2015 at 6:33 AM, Neil Roberts <n...@linux.intel.com> wrote: > Stepping C0 of Skylake fails when using SIMD16 with 3-source > instructions (such as MAD). This patch just makes it disable SIMD16 in > that case. > > This implements WaDisableSIMD16On3SrcInstr and fixes ~190 Piglit > tests. > ---
We already have code in brw_fs_generator.cpp to split SIMD16 instructions into 2x SIMD8 for all of the three-source instructions we support (MAD, LRP, BFE, BFI2). Is there some reason you can't just enable that for these particular Skylake steppings? _______________________________________________ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
