On Sat, Mar 14, 2015 at 9:54 PM, Jordan Justen
<jordan.l.jus...@intel.com> wrote:
> Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com>
> ---
> src/mesa/drivers/dri/i965/brw_fs.cpp | 82
> +++++++++++++++++++++++++++-
> src/mesa/drivers/dri/i965/brw_fs.h | 10 ++++
> src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 23 ++++++++
> 3 files changed, 112 insertions(+), 3 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
> b/src/mesa/drivers/dri/i965/brw_fs.cpp
> index 8702ea8..6427ffb 100644
> --- a/src/mesa/drivers/dri/i965/brw_fs.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
> @@ -1699,9 +1699,15 @@ fs_visitor::assign_curb_setup()
> if (dispatch_width == 8) {
> prog_data->dispatch_grf_start_reg = payload.num_regs;
> } else {
> - assert(stage == MESA_SHADER_FRAGMENT);
> - brw_wm_prog_data *prog_data = (brw_wm_prog_data*) this->prog_data;
> - prog_data->dispatch_grf_start_reg_16 = payload.num_regs;
> + if (stage == MESA_SHADER_FRAGMENT) {
> + brw_wm_prog_data *prog_data = (brw_wm_prog_data*) this->prog_data;
> + prog_data->dispatch_grf_start_reg_16 = payload.num_regs;
> + } else if (stage == MESA_SHADER_COMPUTE) {
> + brw_cs_prog_data *prog_data = (brw_cs_prog_data*) this->prog_data;
> + prog_data->dispatch_grf_start_reg_16 = payload.num_regs;
> + } else {
> + unreachable("Unsupported shader type!");
> + }
> }
>
> prog_data->curb_read_length = ALIGN(stage_prog_data->nr_params, 8) / 8;
> @@ -3634,6 +3640,14 @@ fs_visitor::setup_vs_payload()
> }
>
> void
> +fs_visitor::setup_cs_payload()
> +{
> + assert(brw->gen >= 7);
> +
> + payload.num_regs = 1;
> +}
> +
> +void
> fs_visitor::assign_binding_table_offsets()
> {
> assert(stage == MESA_SHADER_FRAGMENT);
> @@ -3969,6 +3983,68 @@ fs_visitor::run_fs()
> return !failed;
> }
>
> +bool
> +fs_visitor::run_cs()
> +{
> + assert(stage == MESA_SHADER_COMPUTE);
> +
> + sanity_param_count = prog->Parameters->NumParameters;
> +
> + assign_common_binding_table_offsets(0);
> +
> + setup_cs_payload();
> +
> + if (0) {
> + emit_dummy_fs();
> + } else if (brw->use_rep_send && dispatch_width == 16) {
> + emit_repclear_shader();
> + } else {
We don't need the dummy_fs or repclear shaders in run_cs().
Kristian
> + if (INTEL_DEBUG & DEBUG_SHADER_TIME)
> + emit_shader_time_begin();
> +
> + /* Generate CS IR for main(). (the visitor only descends into
> + * functions called "main").
> + */
> + if (shader) {
> + if (getenv("INTEL_USE_NIR") != NULL) {
> + emit_nir_code();
> + } else {
> + foreach_in_list(ir_instruction, ir, shader->base.ir) {
> + base_ir = ir;
> + this->result = reg_undef;
> + ir->accept(this);
> + }
> + }
> + }
> + base_ir = NULL;
> + if (failed)
> + return false;
> +
> + emit_cs_terminate();
> +
> + calculate_cfg();
> +
> + optimize();
> +
> + assign_curb_setup();
> +
> + fixup_3src_null_dest();
> + allocate_registers();
> +
> + if (failed)
> + return false;
> + }
> +
> + /* If any state parameters were appended, then ParameterValues could have
> + * been realloced, in which case the driver uniform storage set up by
> + * _mesa_associate_uniform_storage() would point to freed memory. Make
> + * sure that didn't happen.
> + */
> + assert(sanity_param_count == prog->Parameters->NumParameters);
> +
> + return !failed;
> +}
> +
> const unsigned *
> brw_wm_fs_emit(struct brw_context *brw,
> void *mem_ctx,
> diff --git a/src/mesa/drivers/dri/i965/brw_fs.h
> b/src/mesa/drivers/dri/i965/brw_fs.h
> index b8b26a4..5a243d0 100644
> --- a/src/mesa/drivers/dri/i965/brw_fs.h
> +++ b/src/mesa/drivers/dri/i965/brw_fs.h
> @@ -89,6 +89,14 @@ public:
> struct gl_vertex_program *cp,
> unsigned dispatch_width);
>
> + fs_visitor(struct brw_context *brw,
> + void *mem_ctx,
> + const struct brw_cs_prog_key *key,
> + struct brw_cs_prog_data *prog_data,
> + struct gl_shader_program *shader_prog,
> + struct gl_compute_program *cp,
> + unsigned dispatch_width);
> +
> ~fs_visitor();
> void init();
>
> @@ -189,12 +197,14 @@ public:
>
> bool run_fs();
> bool run_vs();
> + bool run_cs();
> void optimize();
> void allocate_registers();
> void assign_binding_table_offsets();
> void setup_payload_gen4();
> void setup_payload_gen6();
> void setup_vs_payload();
> + void setup_cs_payload();
> void fixup_3src_null_dest();
> void assign_curb_setup();
> void calculate_urb_setup();
> diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
> b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
> index 88df0a2..c3cf6ba 100644
> --- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
> @@ -39,6 +39,7 @@
> #include "brw_context.h"
> #include "brw_eu.h"
> #include "brw_wm.h"
> +#include "brw_cs.h"
> #include "brw_vec4.h"
> #include "brw_fs.h"
> #include "main/uniforms.h"
> @@ -4025,6 +4026,25 @@ fs_visitor::fs_visitor(struct brw_context *brw,
> init();
> }
>
> +fs_visitor::fs_visitor(struct brw_context *brw,
> + void *mem_ctx,
> + const struct brw_cs_prog_key *key,
> + struct brw_cs_prog_data *prog_data,
> + struct gl_shader_program *shader_prog,
> + struct gl_compute_program *cp,
> + unsigned dispatch_width)
> + : backend_visitor(brw, shader_prog, &cp->Base, &prog_data->base,
> + MESA_SHADER_COMPUTE),
> + reg_null_f(retype(brw_null_vec(dispatch_width), BRW_REGISTER_TYPE_F)),
> + reg_null_d(retype(brw_null_vec(dispatch_width), BRW_REGISTER_TYPE_D)),
> + reg_null_ud(retype(brw_null_vec(dispatch_width), BRW_REGISTER_TYPE_UD)),
> + key(key), prog_data(&prog_data->base),
> + dispatch_width(dispatch_width)
> +{
> + this->mem_ctx = mem_ctx;
> + init();
> +}
> +
> void
> fs_visitor::init()
> {
> @@ -4036,6 +4056,9 @@ fs_visitor::init()
> case MESA_SHADER_GEOMETRY:
> key_tex = &((const brw_vue_prog_key *) key)->tex;
> break;
> + case MESA_SHADER_COMPUTE:
> + key_tex = &((const brw_cs_prog_key*) key)->tex;
> + break;
> default:
> unreachable("unhandled shader stage");
> }
> --
> 2.1.4
>
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