Signed-off-by: Topi Pohjolainen <topi.pohjolai...@intel.com>
---
src/mesa/drivers/dri/i965/brw_blorp.cpp | 15 +++++++++
src/mesa/drivers/dri/i965/brw_blorp.h | 41 ++++++++++++++++++++++++
src/mesa/drivers/dri/i965/gen6_blorp.cpp | 22 +++++++++++++
src/mesa/drivers/dri/i965/gen7_blorp.cpp | 54 ++++++++++++++++++++++++++++++++
4 files changed, 132 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.cpp
b/src/mesa/drivers/dri/i965/brw_blorp.cpp
index 680db75..bd080b0 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp.cpp
@@ -335,3 +335,18 @@ brw_hiz_op_params::brw_hiz_op_params(struct
intel_mipmap_tree *mt,
default: unreachable("not reached");
}
}
+
+/**
+ * Set relevant fields such as normal gl-state based program loading would.
+ */
+struct brw_stage_state
+brw_meta_fs_params::create_stage_state(const struct gl_fragment_program *fp,
+ uint32_t wm_prog_offset)
+{
+ struct brw_stage_state res;
+ res.stage = MESA_SHADER_FRAGMENT;
+ res.scratch_bo = NULL;
+ res.sampler_count = _mesa_fls(fp->Base.SamplersUsed);
+ res.prog_offset = wm_prog_offset;
+ return res;
+}
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.h
b/src/mesa/drivers/dri/i965/brw_blorp.h
index 2abe654..aa83c66 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.h
+++ b/src/mesa/drivers/dri/i965/brw_blorp.h
@@ -388,6 +388,47 @@ private:
uint32_t sampler_offset;
};
+class brw_meta_fs_params : public brw_blorp_params
+{
+public:
+ brw_meta_fs_params(unsigned dst_num_samples,
+ unsigned num_draw_buffers, unsigned num_layers,
+ const struct gl_fragment_program *fp,
+ uint32_t wm_prog_offset,
+ const struct brw_wm_prog_data *wm_prog_data,
+ unsigned fast_clear_op)
+ : brw_blorp_params(wm_prog_data->num_varying_inputs,
+ num_draw_buffers, num_layers),
+ dst_num_samples(dst_num_samples), fp(fp), wm_prog_data(wm_prog_data),
+ wm_prog_offset(wm_prog_offset), fast_clear_op(fast_clear_op),
+ wm_stage_state(create_stage_state(fp, wm_prog_offset))
+ {
+ }
+
+ virtual void gen6_emit_wm_constants(struct brw_context *brw);
+
+ virtual void gen7_emit_wm_config(struct brw_context *brw) const;
+
+ virtual void gen6_emit_multisample_state(struct brw_context *brw) const;
+
+ virtual void gen7_emit_ps_config(struct brw_context *brw) const;
+
+protected:
+ const unsigned dst_num_samples;
+ const struct gl_fragment_program * const fp;
+ const struct brw_wm_prog_data * const wm_prog_data;
+ const uint32_t wm_prog_offset;
+ const unsigned fast_clear_op;
+ struct brw_stage_state wm_stage_state;
+ uint32_t wm_bind_bo_offset;
+ uint32_t sampler_offset;
+
+private:
+ static struct brw_stage_state create_stage_state(
+ const struct gl_fragment_program *fp,
+ uint32_t wm_prog_offset);
+};
+
/**
* \name BLORP internals
* \{
diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
index 77de474..39d32df 100644
--- a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
@@ -1081,6 +1081,28 @@ brw_blorp_blit_params::gen6_emit_sampler_state(struct
brw_context *brw) const
gen6_blorp_emit_sampler_state_pointers(brw, sampler_offset);
}
+void
+brw_meta_fs_params::gen6_emit_wm_constants(struct brw_context *brw)
+{
+ gen6_upload_push_constants(brw, &fp->Base, &wm_prog_data->base,
+ &wm_stage_state, AUB_TRACE_WM_CONSTANTS);
+
+ if (brw->gen >= 7) {
+ gen7_upload_constant_state(brw, &wm_stage_state, true,
+ _3DSTATE_CONSTANT_PS);
+ }
+}
+
+void
+brw_meta_fs_params::gen6_emit_multisample_state(struct brw_context *brw) const
+{
+ const unsigned sample_mask =
+ dst_num_samples > 1 ? (1 << dst_num_samples) - 1 : 1;
+
+ gen6_emit_3dstate_multisample(brw, dst_num_samples);
+ gen6_emit_3dstate_sample_mask(brw, sample_mask);
+}
+
/**
* \brief Execute a blit or render pass operation.
*
diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
index f430fa0..f52937b 100644
--- a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
@@ -478,6 +478,39 @@ gen7_blorp_emit_wm_config(struct brw_context *brw,
ADVANCE_BATCH();
}
+static void
+gen7_blorp_upload_wm_state(struct brw_context *brw,
+ const struct gl_fragment_program *fp,
+ const struct brw_wm_prog_data *prog_data,
+ bool multisampled_fbo)
+{
+ uint32_t dw1, dw2;
+
+ dw1 = dw2 = 0;
+ dw1 |= GEN7_WM_LINE_AA_WIDTH_1_0;
+ dw1 |= GEN7_WM_LINE_END_CAP_AA_WIDTH_0_5;
+
+ dw1 |= prog_data->computed_depth_mode << GEN7_WM_COMPUTED_DEPTH_MODE_SHIFT;
+ dw1 |= prog_data->barycentric_interp_modes <<
+ GEN7_WM_BARYCENTRIC_INTERPOLATION_MODE_SHIFT;
+
+ if (prog_data->uses_kill | prog_data->uses_omask)
+ dw1 |= GEN7_WM_KILL_ENABLE;
+
+ dw1 |= GEN7_WM_DISPATCH_ENABLE;
+
+ dw1 |= GEN7_WM_MSRAST_OFF_PIXEL;
+ if (multisampled_fbo)
+ dw2 |= GEN7_WM_MSDISPMODE_PERPIXEL;
+ else
+ dw2 |= GEN7_WM_MSDISPMODE_PERSAMPLE;
+
+ BEGIN_BATCH(3);
+ OUT_BATCH(_3DSTATE_WM << 16 | (3 - 2));
+ OUT_BATCH(dw1);
+ OUT_BATCH(dw2);
+ ADVANCE_BATCH();
+}
/**
* 3DSTATE_PS
@@ -804,6 +837,27 @@ brw_blorp_blit_params::gen7_emit_ps_config(struct
brw_context *brw) const
gen7_blorp_emit_ps_config(brw, this, prog_offset, prog_data);
}
+void
+brw_meta_fs_params::gen7_emit_wm_config(struct brw_context *brw) const
+{
+ const bool multisampled_fbo = dst_num_samples > 1;
+ gen7_blorp_upload_wm_state(brw, fp, wm_prog_data, multisampled_fbo);
+}
+
+void
+brw_meta_fs_params::gen7_emit_ps_config(struct brw_context *brw) const
+{
+ /* Neither meta clears or blits use any special sample coverage or
+ * mask settings. Hence the mask for hardware can be fixed to the default.
+ * Nor do the meta programs take advantage of dual source blending.
+ */
+ const unsigned default_sample_mask = 1;
+ const bool enable_dual_src_blend = false;
+ gen7_upload_ps_state(brw, fp, &wm_stage_state, wm_prog_data,
+ enable_dual_src_blend, default_sample_mask,
+ fast_clear_op);
+}
+
/**
* \copydoc gen6_blorp_exec()
*/
--
1.9.3
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