On Thu, May 07, 2015 at 05:52:12PM +0300, Pohjolainen, Topi wrote:
> On Tue, Apr 28, 2015 at 11:08:06PM +0300, Abdiel Janulgue wrote:
> > Reserve space in the gather pool where the gathered uniforms are flushed.
> >
> > Signed-off-by: Abdiel Janulgue <abdiel.janul...@linux.intel.com>
> > ---
> > src/mesa/drivers/dri/i965/gen6_vs_state.c | 8 ++++++++
> > 1 file changed, 8 insertions(+)
> >
> > diff --git a/src/mesa/drivers/dri/i965/gen6_vs_state.c
> > b/src/mesa/drivers/dri/i965/gen6_vs_state.c
> > index 35d10ef..aebaa49 100644
> > --- a/src/mesa/drivers/dri/i965/gen6_vs_state.c
> > +++ b/src/mesa/drivers/dri/i965/gen6_vs_state.c
> > @@ -120,6 +120,14 @@ gen6_upload_push_constants(struct brw_context *brw,
> > */
> > assert(stage_state->push_const_size <= 32);
> > }
> > + /* Allocate gather pool space for uniform and UBO entries in 512-bit
> > chunks*/
> > + if (brw->gather_pool.bo != NULL) {
> > + if (prog_data->nr_params > 0) {
>
> I guess you combine these conditions:
>
> if (brw->gather_pool.bo != NULL && prog_data->nr_params > 0)
>
> Or even bail out early:
Newermind, you modify it even further in the next patch.
>
> if (brw->gather_pool.bo == NULL || prog_data->nr_params == 0)
> return;
>
> > + int num_consts = ALIGN(prog_data->nr_params, 4) / 4;
>
> This could be const, no big deal though.
>
> > + stage_state->push_const_offset = brw->gather_pool.next_offset;
> > + brw->gather_pool.next_offset += (ALIGN(num_consts, 4) / 4) * 64;
> > + }
> > + }
> > }
> >
> > static void
> > --
> > 1.9.1
> >
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