Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk>
---
src/mesa/drivers/dri/i965/brw_blorp.cpp | 16 +++++++++-------
src/mesa/drivers/dri/i965/brw_clear.c | 11 +----------
src/mesa/drivers/dri/i965/brw_context.c | 4 +++-
src/mesa/drivers/dri/i965/brw_context.h | 2 ++
src/mesa/drivers/dri/i965/brw_draw.c | 2 +-
src/mesa/drivers/dri/i965/brw_meta_fast_clear.c | 7 +++----
src/mesa/drivers/dri/i965/brw_meta_stencil_blit.c | 8 ++++----
src/mesa/drivers/dri/i965/brw_meta_updownsample.c | 6 ++----
src/mesa/drivers/dri/i965/brw_misc_state.c | 4 ++--
src/mesa/drivers/dri/i965/brw_pipe_control.c | 1 +
src/mesa/drivers/dri/i965/brw_state_upload.c | 1 +
src/mesa/drivers/dri/i965/intel_blit.c | 6 +++---
src/mesa/drivers/dri/i965/intel_buffer_objects.c | 4 ++--
src/mesa/drivers/dri/i965/intel_pixel_read.c | 2 +-
src/mesa/drivers/dri/i965/intel_tex_image.c | 2 +-
15 files changed, 36 insertions(+), 40 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.cpp
b/src/mesa/drivers/dri/i965/brw_blorp.cpp
index d4d5457..34c0e3c 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp.cpp
@@ -220,6 +220,13 @@ brw_blorp_exec(struct brw_context *brw, const
brw_blorp_params *params)
* docs to flush the cache between reinterpretations of the same surface
* data with different formats, which blorp does for stencil and depth
* data.
+ *
+ * From the Sandy Bridge PRM, volume 2 part 1, page 313:
+ *
+ * "If other rendering operations have preceded this clear, a
+ * PIPE_CONTROL with write cache flush enabled and Z-inhibit disabled
+ * must be issued before the rectangle primitive used for the depth
+ * buffer clear operation.
*/
brw_emit_mi_flush(brw);
@@ -235,11 +242,6 @@ brw_blorp_exec(struct brw_context *brw, const
brw_blorp_params *params)
unreachable("not reached");
}
- /* Flush the sampler cache so any texturing from the destination is
- * coherent.
- */
- brw_emit_mi_flush(brw);
-
/* Check if the blorp op we just did would make our batch likely to fail to
* map all the BOs into the GPU at batch exec time later. If so, flush the
* batch and try again with nothing else in the batch.
@@ -249,14 +251,14 @@ brw_blorp_exec(struct brw_context *brw, const
brw_blorp_params *params)
return;
}
- brw_batch_maybe_flush(&brw->batch);
-
/* We've smashed all state compared to what the normal 3D pipeline
* rendering tracks for GL.
*/
brw->ctx.NewDriverState = ~0ull;
brw->no_depth_or_stencil = false;
brw->ib.type = -1;
+
+ brw_batch_maybe_flush(&brw->batch);
}
brw_hiz_op_params::brw_hiz_op_params(struct intel_mipmap_tree *mt,
diff --git a/src/mesa/drivers/dri/i965/brw_clear.c
b/src/mesa/drivers/dri/i965/brw_clear.c
index 3bf2d6d..474690a 100644
--- a/src/mesa/drivers/dri/i965/brw_clear.c
+++ b/src/mesa/drivers/dri/i965/brw_clear.c
@@ -176,15 +176,6 @@ brw_fast_clear_depth(struct gl_context *ctx)
mt->depth_clear_value = depth_clear_value;
}
- /* From the Sandy Bridge PRM, volume 2 part 1, page 313:
- *
- * "If other rendering operations have preceded this clear, a
- * PIPE_CONTROL with write cache flush enabled and Z-inhibit disabled
- * must be issued before the rectangle primitive used for the depth
- * buffer clear operation.
- */
- brw_mi_flush(brw, RENDER_RING);
-
if (fb->MaxNumLayers > 0) {
for (unsigned layer = 0; layer < depth_irb->layer_count; layer++) {
intel_hiz_exec(brw, mt, depth_irb->mt_level,
@@ -203,7 +194,7 @@ brw_fast_clear_depth(struct gl_context *ctx)
* by a PIPE_CONTROL command with DEPTH_STALL bit set and Then
* followed by Depth FLUSH'
*/
- brw_mi_flush(brw, RENDER_RING);
+ brw->ctx.NewDriverState |= BRW_NEW_CACHE_FLUSH;
}
/* Now, the HiZ buffer contains data that needs to be resolved to the depth
diff --git a/src/mesa/drivers/dri/i965/brw_context.c
b/src/mesa/drivers/dri/i965/brw_context.c
index a51fd81..ad5926a 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -187,7 +187,7 @@ intel_update_state(struct gl_context * ctx, GLuint
new_state)
intel_miptree_all_slices_resolve_depth(brw, tex_obj->mt);
intel_miptree_resolve_color(brw, tex_obj->mt);
if (brw_check_dirty(tex_obj->mt->bo))
- brw_mi_flush(brw, RENDER_RING);
+ brw->ctx.NewDriverState |= BRW_NEW_CACHE_FLUSH;
}
_mesa_lock_context_textures(ctx);
@@ -1537,6 +1537,8 @@ void brw_batch_finish_hook(brw_batch *batch)
{
struct brw_context *brw = container_of(batch, brw, batch);
+ brw->ctx.NewDriverState &= ~BRW_NEW_CACHE_FLUSH;
+
if (batch->ring != RENDER_RING)
return;
diff --git a/src/mesa/drivers/dri/i965/brw_context.h
b/src/mesa/drivers/dri/i965/brw_context.h
index cf91234..868fa13 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -213,6 +213,7 @@ enum brw_state_id {
BRW_STATE_SAMPLER_STATE_TABLE,
BRW_STATE_VS_ATTRIB_WORKAROUNDS,
BRW_STATE_COMPUTE_PROGRAM,
+ BRW_STATE_CACHE_FLUSH,
BRW_NUM_STATE_BITS
};
@@ -294,6 +295,7 @@ enum brw_state_id {
#define BRW_NEW_SAMPLER_STATE_TABLE (1ull << BRW_STATE_SAMPLER_STATE_TABLE)
#define BRW_NEW_VS_ATTRIB_WORKAROUNDS (1ull <<
BRW_STATE_VS_ATTRIB_WORKAROUNDS)
#define BRW_NEW_COMPUTE_PROGRAM (1ull << BRW_STATE_COMPUTE_PROGRAM)
+#define BRW_NEW_CACHE_FLUSH (1ull << BRW_STATE_CACHE_FLUSH)
struct brw_state_flags {
/** State update flags signalled by mesa internals */
diff --git a/src/mesa/drivers/dri/i965/brw_draw.c
b/src/mesa/drivers/dri/i965/brw_draw.c
index 4cc4586..09b2f15 100644
--- a/src/mesa/drivers/dri/i965/brw_draw.c
+++ b/src/mesa/drivers/dri/i965/brw_draw.c
@@ -215,7 +215,7 @@ brw_emit_prim(struct brw_context *brw,
* and missed flushes of the render cache as it heads to other parts of
* the besides the draw code.
*/
- if (brw->always_flush_cache)
+ if (brw->always_flush_cache || brw->ctx.NewDriverState &
BRW_NEW_CACHE_FLUSH)
brw_emit_mi_flush(brw);
/* If indirect, emit a bunch of loads from the indirect BO. */
diff --git a/src/mesa/drivers/dri/i965/brw_meta_fast_clear.c
b/src/mesa/drivers/dri/i965/brw_meta_fast_clear.c
index 294378a..e650ac6 100644
--- a/src/mesa/drivers/dri/i965/brw_meta_fast_clear.c
+++ b/src/mesa/drivers/dri/i965/brw_meta_fast_clear.c
@@ -524,7 +524,7 @@ brw_meta_fast_clear(struct brw_context *brw, struct
gl_framebuffer *fb,
* we draw, in case the mt is also bound as a texture.
*/
irb->mt->fast_clear_state = INTEL_FAST_CLEAR_STATE_RESOLVED;
- irb->need_downsample = true;
+ ctx->NewDriverState |= BRW_NEW_CACHE_FLUSH;
fast_clear_buffers |= 1 << index;
get_fast_clear_rect(brw, fb, irb, &fast_clear_rect);
break;
@@ -633,7 +633,7 @@ brw_meta_fast_clear(struct brw_context *brw, struct
gl_framebuffer *fb,
* write-flush must be issued before sending any DRAW commands on that
* render target.
*/
- brw_mi_flush(brw, RENDER_RING);
+ ctx->NewDriverState |= BRW_NEW_CACHE_FLUSH;
/* If we had to fall back to plain clear for any buffers, clear those now
* by calling into meta.
@@ -687,8 +687,6 @@ brw_meta_resolve_color(struct brw_context *brw,
GLuint fbo, rbo;
struct rect rect;
- brw_mi_flush(brw, RENDER_RING);
-
_mesa_meta_begin(ctx, MESA_META_ALL);
_mesa_GenFramebuffers(1, &fbo);
@@ -709,6 +707,7 @@ brw_meta_resolve_color(struct brw_context *brw,
set_fast_clear_op(brw, GEN7_PS_RENDER_TARGET_RESOLVE_ENABLE);
mt->fast_clear_state = INTEL_FAST_CLEAR_STATE_RESOLVED;
+ ctx->NewDriverState |= BRW_NEW_CACHE_FLUSH;
get_resolve_rect(brw, mt, &rect);
brw_draw_rectlist(ctx, &rect, 1);
diff --git a/src/mesa/drivers/dri/i965/brw_meta_stencil_blit.c
b/src/mesa/drivers/dri/i965/brw_meta_stencil_blit.c
index 840d9d3..f13a8b7 100644
--- a/src/mesa/drivers/dri/i965/brw_meta_stencil_blit.c
+++ b/src/mesa/drivers/dri/i965/brw_meta_stencil_blit.c
@@ -499,11 +499,11 @@ brw_meta_fbo_stencil_blit(struct brw_context *brw,
.mirror_x = mirror_x, .mirror_y = mirror_y };
adjust_mip_level(dst_mt, dst_irb->mt_level, dst_irb->mt_layer, &dims);
- brw_mi_flush(brw, RENDER_RING);
+ ctx->NewDriverState |= BRW_NEW_CACHE_FLUSH;
_mesa_meta_begin(ctx, MESA_META_ALL);
brw_meta_stencil_blit(brw,
dst_mt, dst_irb->mt_level, dst_irb->mt_layer, &dims);
- brw_mi_flush(brw, RENDER_RING);
+ ctx->NewDriverState |= BRW_NEW_CACHE_FLUSH;
}
void
@@ -523,7 +523,7 @@ brw_meta_stencil_updownsample(struct brw_context *brw,
if (dst->stencil_mt)
dst = dst->stencil_mt;
- brw_mi_flush(brw, RENDER_RING);
+ ctx->NewDriverState |= BRW_NEW_CACHE_FLUSH;
_mesa_meta_begin(ctx, MESA_META_ALL);
_mesa_GenFramebuffers(1, &fbo);
@@ -534,7 +534,7 @@ brw_meta_stencil_updownsample(struct brw_context *brw,
GL_RENDERBUFFER, rbo);
brw_meta_stencil_blit(brw, dst, 0, 0, &dims);
- brw_mi_flush(brw, RENDER_RING);
+ ctx->NewDriverState |= BRW_NEW_CACHE_FLUSH;
_mesa_DeleteRenderbuffers(1, &rbo);
_mesa_DeleteFramebuffers(1, &fbo);
diff --git a/src/mesa/drivers/dri/i965/brw_meta_updownsample.c
b/src/mesa/drivers/dri/i965/brw_meta_updownsample.c
index c6dd822..3dc755d 100644
--- a/src/mesa/drivers/dri/i965/brw_meta_updownsample.c
+++ b/src/mesa/drivers/dri/i965/brw_meta_updownsample.c
@@ -115,8 +115,7 @@ brw_meta_updownsample(struct brw_context *brw,
blit_bit = GL_COLOR_BUFFER_BIT;
}
- brw_mi_flush(brw, RENDER_RING);
-
+ ctx->NewDriverState |= BRW_NEW_CACHE_FLUSH;
_mesa_meta_begin(ctx, MESA_META_ALL);
_mesa_GenFramebuffers(2, fbos);
src_rbo = brw_get_rb_for_slice(brw, src_mt, 0, 0, false);
@@ -145,6 +144,5 @@ brw_meta_updownsample(struct brw_context *brw,
_mesa_DeleteFramebuffers(2, fbos);
_mesa_meta_end(ctx);
-
- brw_mi_flush(brw, RENDER_RING);
+ ctx->NewDriverState |= BRW_NEW_CACHE_FLUSH;
}
diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c
b/src/mesa/drivers/dri/i965/brw_misc_state.c
index 85f41f9..466521c 100644
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -547,9 +547,9 @@ brw_emit_depthbuffer(struct brw_context *brw)
}
if (depth_mt && brw_check_dirty(depth_mt->bo))
- brw_emit_mi_flush(brw);
+ brw->ctx.NewDriverState |= BRW_NEW_CACHE_FLUSH;
if (stencil_mt && brw_check_dirty(stencil_mt->bo))
- brw_emit_mi_flush(brw);
+ brw->ctx.NewDriverState |= BRW_NEW_CACHE_FLUSH;
brw->vtbl.emit_depth_stencil_hiz(brw, depth_mt, depth_offset,
depthbuffer_format, depth_surface_type,
diff --git a/src/mesa/drivers/dri/i965/brw_pipe_control.c
b/src/mesa/drivers/dri/i965/brw_pipe_control.c
index f6bdcc8..589ec69 100644
--- a/src/mesa/drivers/dri/i965/brw_pipe_control.c
+++ b/src/mesa/drivers/dri/i965/brw_pipe_control.c
@@ -328,6 +328,7 @@ brw_emit_mi_flush(struct brw_context *brw)
}
brw_batch_clear_dirty(&brw->batch);
+ brw->ctx.NewDriverState &= ~BRW_NEW_CACHE_FLUSH;
}
void
diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c
b/src/mesa/drivers/dri/i965/brw_state_upload.c
index ea15f9d..1c26dda 100644
--- a/src/mesa/drivers/dri/i965/brw_state_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
@@ -604,6 +604,7 @@ static struct dirty_bit_map brw_bits[] = {
DEFINE_BIT(BRW_NEW_SAMPLER_STATE_TABLE),
DEFINE_BIT(BRW_NEW_VS_ATTRIB_WORKAROUNDS),
DEFINE_BIT(BRW_NEW_COMPUTE_PROGRAM),
+ DEFINE_BIT(BRW_NEW_CACHE_FLUSH),
{0, 0, 0}
};
diff --git a/src/mesa/drivers/dri/i965/intel_blit.c
b/src/mesa/drivers/dri/i965/intel_blit.c
index 8c1bd49..d95e5aa5 100644
--- a/src/mesa/drivers/dri/i965/intel_blit.c
+++ b/src/mesa/drivers/dri/i965/intel_blit.c
@@ -667,7 +667,7 @@ intelEmitCopyBlit(struct brw_context *brw,
ADVANCE_BATCH_TILED(dst_y_tiled, src_y_tiled);
- brw_emit_mi_flush(brw);
+ brw->ctx.NewDriverState |= BRW_NEW_CACHE_FLUSH;
return brw_batch_end(&brw->batch) == 0;
}
@@ -747,7 +747,7 @@ intelEmitImmediateColorExpandBlit(struct brw_context *brw,
brw_batch_data(&brw->batch, src_bits, dwords * 4);
- brw_emit_mi_flush(brw);
+ brw->ctx.NewDriverState |= BRW_NEW_CACHE_FLUSH;
return brw_batch_end(&brw->batch) == 0;
}
@@ -863,7 +863,7 @@ intel_miptree_set_alpha_to_one(struct brw_context *brw,
OUT_BATCH(0xffffffff); /* white, but only alpha gets written */
ADVANCE_BATCH_TILED(dst_y_tiled, false);
- brw_emit_mi_flush(brw);
+ brw->ctx.NewDriverState |= BRW_NEW_CACHE_FLUSH;
brw_batch_end(&brw->batch);
}
diff --git a/src/mesa/drivers/dri/i965/intel_buffer_objects.c
b/src/mesa/drivers/dri/i965/intel_buffer_objects.c
index e0566b0..1d01d32 100644
--- a/src/mesa/drivers/dri/i965/intel_buffer_objects.c
+++ b/src/mesa/drivers/dri/i965/intel_buffer_objects.c
@@ -488,7 +488,7 @@ brw_unmap_buffer(struct gl_context *ctx,
* flush. Once again, we wish for a domain tracker in libdrm to cover
* usage inside of a batchbuffer.
*/
- brw_mi_flush(brw, BLT_RING);
+ ctx->NewDriverState |= BRW_NEW_CACHE_FLUSH;
brw_bo_put(intel_obj->range_map_bo[index]);
intel_obj->range_map_bo[index] = NULL;
@@ -558,7 +558,7 @@ brw_copy_buffer_subdata(struct gl_context *ctx,
* flush. Once again, we wish for a domain tracker in libdrm to cover
* usage inside of a batchbuffer.
*/
- brw_mi_flush(brw, BLT_RING);
+ ctx->NewDriverState |= BRW_NEW_CACHE_FLUSH;
}
void
diff --git a/src/mesa/drivers/dri/i965/intel_pixel_read.c
b/src/mesa/drivers/dri/i965/intel_pixel_read.c
index 7b86f9c..5765027 100644
--- a/src/mesa/drivers/dri/i965/intel_pixel_read.c
+++ b/src/mesa/drivers/dri/i965/intel_pixel_read.c
@@ -232,7 +232,7 @@ intelReadPixels(struct gl_context * ctx,
* rendered to via a PBO at any point, so it seems better to just
* flush here unconditionally.
*/
- brw_mi_flush(brw, BLT_RING);
+ brw->ctx.NewDriverState |= BRW_NEW_CACHE_FLUSH;
return;
}
diff --git a/src/mesa/drivers/dri/i965/intel_tex_image.c
b/src/mesa/drivers/dri/i965/intel_tex_image.c
index 553f0b0..d0a4555 100644
--- a/src/mesa/drivers/dri/i965/intel_tex_image.c
+++ b/src/mesa/drivers/dri/i965/intel_tex_image.c
@@ -482,7 +482,7 @@ intel_get_tex_sub_image(struct gl_context *ctx,
* See the related comment in intelReadPixels() for a more detailed
* explanation.
*/
- brw_mi_flush(brw, BLT_RING);
+ brw->ctx.NewDriverState |= BRW_NEW_CACHE_FLUSH;
return;
}
--
2.5.0
_______________________________________________
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev
