On Mon, Aug 31, 2015 at 4:45 PM, Nanley Chery <nanleych...@gmail.com> wrote:
> From: Nanley Chery <nanley.g.ch...@intel.com>
>
> Add modifications necessary to get ASTC functional on Cherryview.
>
> Cc: Chad Versace <chad.vers...@intel.com>
> Signed-off-by: Nanley Chery <nanley.g.ch...@intel.com>
> ---
> src/mesa/drivers/dri/i965/brw_defines.h | 1 +
> src/mesa/drivers/dri/i965/brw_tex_layout.c | 55
> +++++++++++++++++++-------
> src/mesa/drivers/dri/i965/gen8_surface_state.c | 6 +++
> src/mesa/drivers/dri/i965/intel_extensions.c | 4 +-
> 4 files changed, 51 insertions(+), 15 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_defines.h
> b/src/mesa/drivers/dri/i965/brw_defines.h
> index 07fe198..4f3092f 100644
> --- a/src/mesa/drivers/dri/i965/brw_defines.h
> +++ b/src/mesa/drivers/dri/i965/brw_defines.h
> @@ -537,6 +537,7 @@
> #define BRW_SURFACEFORMAT_ASTC_LDR_2D_12x10_FLT16 0x27E
> #define BRW_SURFACEFORMAT_ASTC_LDR_2D_12x12_FLT16 0x27F
>
> +#define BRW_SURFACE_FORMAT_IS_ASTC(format) ((format) & 0x200)
> #define BRW_SURFACE_FORMAT_SHIFT 18
> #define BRW_SURFACE_FORMAT_MASK INTEL_MASK(26, 18)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c
> b/src/mesa/drivers/dri/i965/brw_tex_layout.c
> index 268b995..a08e0ab 100644
> --- a/src/mesa/drivers/dri/i965/brw_tex_layout.c
> +++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c
> @@ -34,6 +34,8 @@
>
> #include "intel_mipmap_tree.h"
> #include "brw_context.h"
> +#include "brw_defines.h"
> +#include "brw_state.h"
> #include "main/macros.h"
> #include "main/glformats.h"
>
> @@ -302,8 +304,17 @@ gen9_miptree_layout_1d(struct intel_mipmap_tree *mt)
> }
> }
>
> +static inline bool
> +is_astc_chv(const struct brw_context *brw,
> + const struct intel_mipmap_tree *mt)
> +{
> + return brw->is_cherryview &&
> + BRW_SURFACE_FORMAT_IS_ASTC(brw_format_for_mesa_format(mt->format));
> +}
> +
> static void
> -brw_miptree_layout_2d(struct intel_mipmap_tree *mt)
> +brw_miptree_layout_2d(const struct brw_context *brw,
> + struct intel_mipmap_tree *mt)
> {
> unsigned x = 0;
> unsigned y = 0;
> @@ -335,6 +346,17 @@ brw_miptree_layout_2d(struct intel_mipmap_tree *mt)
> minify(mt->physical_width0, 2);
> }
>
> + /* Cherryview requires that all miplevels get shifted over 3 blocks
> for
> + * ASTC formats with block width of 5 and certain mip1 widths.
> + */
> + if (is_astc_chv(brw, mt) && bw == 5) {
> + unsigned int mip1_width_mod = minify(mt->physical_width0, 1) % 10;
> + if (mip1_width_mod && mip1_width_mod <= bw) {
> + x = 3;
> + mip1_width += x*bw;
> + }
> + }
> +
> if (mip1_width > mt->total_width) {
> mt->total_width = mip1_width;
> }
> @@ -481,7 +503,7 @@ brw_miptree_layout_texture_array(struct brw_context *brw,
> if (layout_1d)
> gen9_miptree_layout_1d(mt);
> else
> - brw_miptree_layout_2d(mt);
> + brw_miptree_layout_2d(brw, mt);
>
> if (layout_1d) {
> physical_qpitch = 1;
> @@ -492,12 +514,18 @@ brw_miptree_layout_texture_array(struct brw_context
> *brw,
> */
> mt->qpitch = mt->total_width;
> } else {
> - mt->qpitch = brw_miptree_get_vertical_slice_pitch(brw, mt, 0);
> +
> /* Unlike previous generations the qpitch is a multiple of the
> * compressed block size on Gen9 so physical_qpitch matches mt->qpitch.
> */
> - physical_qpitch = (mt->compressed && brw->gen < 9 ? mt->qpitch / 4 :
> - mt->qpitch);
> + physical_qpitch = mt->qpitch =
> brw_miptree_get_vertical_slice_pitch(brw, mt, 0);
> +
> + if (mt->compressed && brw->gen < 9) {
> + unsigned bh, bw;
> + _mesa_get_format_block_size(mt->format, &bw, &bh);
> + physical_qpitch /= bh;
> + }
> +
> }
>
> for (unsigned level = mt->first_level; level <= mt->last_level; level++) {
> @@ -705,7 +733,7 @@ intel_miptree_set_total_width_height(struct brw_context
> *brw,
> if (gen9_use_linear_1d_layout(brw, mt))
> gen9_miptree_layout_1d(mt);
> else
> - brw_miptree_layout_2d(mt);
> + brw_miptree_layout_2d(brw, mt);
> break;
> }
> break;
> @@ -772,7 +800,10 @@ intel_miptree_set_alignment(struct brw_context *brw,
> if (brw->gen >= 9) {
> mt->align_w *= 4;
> mt->align_h *= 4;
> + } else if (is_astc_chv(brw, mt)) {
> + mt->align_h *= 4;
> }
> +
> } else if (mt->format == MESA_FORMAT_S_UINT8) {
> mt->align_w = 8;
> mt->align_h = brw->gen >= 7 ? 8 : 4;
> @@ -803,14 +834,10 @@ brw_miptree_layout(struct brw_context *brw,
> return;
> }
>
> - /* On Gen9+ the alignment values are expressed in multiples of the block
> - * size
> - */
> - if (brw->gen >= 9) {
> - unsigned int i, j;
> - _mesa_get_format_block_size(mt->format, &i, &j);
> - mt->align_w /= i;
> - mt->align_h /= j;
> + /* On CHV and Gen9+ scale down the alignment to valid values for HW */
> + if (mt->compressed && (brw->gen >= 9 || is_astc_chv(brw, mt))) {
> + mt->align_w = 4;
> + mt->align_h = 4;
> }
>
> if ((layout_flags & MIPTREE_LAYOUT_FOR_BO) == 0)
> diff --git a/src/mesa/drivers/dri/i965/gen8_surface_state.c
> b/src/mesa/drivers/dri/i965/gen8_surface_state.c
> index d2f333f..9fb3569 100644
> --- a/src/mesa/drivers/dri/i965/gen8_surface_state.c
> +++ b/src/mesa/drivers/dri/i965/gen8_surface_state.c
> @@ -273,6 +273,12 @@ gen8_emit_texture_surface_state(struct brw_context *brw,
> surf[5] |= SET_FIELD(tr_mode, GEN9_SURFACE_TRMODE);
> /* Disable Mip Tail by setting a large value. */
> surf[5] |= SET_FIELD(15, GEN9_SURFACE_MIP_TAIL_START_LOD);
> + } else if (brw->is_cherryview && BRW_SURFACE_FORMAT_IS_ASTC(format)) {
> + unsigned int bw, bh;
> + unsigned int mip1_width_mod = minify(mt->physical_width0, 1) % 10;
> + _mesa_get_format_block_size(mt->format, &bw, &bh);
> + if (bw == 5 && mip1_width_mod && mip1_width_mod <= bw)
> + surf[5] |= SET_FIELD(4, BRW_SURFACE_X_OFFSET);
> }
>
> if (aux_mt) {
> diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c
> b/src/mesa/drivers/dri/i965/intel_extensions.c
> index 3c764be..18ab048 100644
> --- a/src/mesa/drivers/dri/i965/intel_extensions.c
> +++ b/src/mesa/drivers/dri/i965/intel_extensions.c
> @@ -354,8 +354,10 @@ intelInitExtensions(struct gl_context *ctx)
> ctx->Extensions.ARB_stencil_texturing = true;
> }
>
> - if (brw->gen >= 9) {
> + if (brw->is_cherryview || brw->gen >=9 )
Space between >= and 9
(what's this patch against? I don't have this in my tree)
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