Signed-off-by: Eric Ruei <[email protected]> --- ...e-drm-add-tilcdc-and-tidss-to-drm_modules.patch | 28 ++++++++++++++++++++++ .../recipes-benchmark/glmark2/glmark2_git.bb | 1 + 2 files changed, 29 insertions(+) create mode 100644 meta-arago-extras/recipes-benchmark/glmark2/files/0001-native-state-drm-add-tilcdc-and-tidss-to-drm_modules.patch
diff --git a/meta-arago-extras/recipes-benchmark/glmark2/files/0001-native-state-drm-add-tilcdc-and-tidss-to-drm_modules.patch b/meta-arago-extras/recipes-benchmark/glmark2/files/0001-native-state-drm-add-tilcdc-and-tidss-to-drm_modules.patch new file mode 100644 index 0000000..a66df92 --- /dev/null +++ b/meta-arago-extras/recipes-benchmark/glmark2/files/0001-native-state-drm-add-tilcdc-and-tidss-to-drm_modules.patch @@ -0,0 +1,28 @@ +From b533b3a738b49aa8ca0ad31a3a1ae7e62f0cc883 Mon Sep 17 00:00:00 2001 +From: Eric Ruei <[email protected]> +Date: Thu, 18 Oct 2018 14:06:24 -0400 +Subject: [PATCH] native-state-drm: add tilcdc and tidss to drm_modules list + +Upstream-Status: Pending + +Signed-off-by: Eric Ruei <[email protected]> +--- + src/native-state-drm.cpp | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/src/native-state-drm.cpp b/src/native-state-drm.cpp +index 5f4699f..ef369b0 100644 +--- a/src/native-state-drm.cpp ++++ b/src/native-state-drm.cpp +@@ -207,6 +207,8 @@ NativeStateDRM::init() + "radeon", + "vmgfx", + "omapdrm", ++ "tilcdc", ++ "tidss", + "exynos", + "pl111", + "vc4", +-- +1.9.1 + diff --git a/meta-arago-extras/recipes-benchmark/glmark2/glmark2_git.bb b/meta-arago-extras/recipes-benchmark/glmark2/glmark2_git.bb index 85d7bf1..d7744ad 100644 --- a/meta-arago-extras/recipes-benchmark/glmark2/glmark2_git.bb +++ b/meta-arago-extras/recipes-benchmark/glmark2/glmark2_git.bb @@ -18,6 +18,7 @@ SRC_URI = "git://github.com/glmark2/glmark2.git;protocol=https \ file://build-Check-packages-to-be-used-by-the-enabled-flavo.patch \ file://0001-Fix-wl_surface-should-be-destoryed-after-the-wl_wind.patch \ file://Fix-configure-for-sqrt-check.patch \ + file://0001-native-state-drm-add-tilcdc-and-tidss-to-drm_modules.patch \ " SRCREV = "9b1070fe9c5cf908f323909d3c8cbed08022abe8" -- 1.9.1 _______________________________________________ meta-arago mailing list [email protected] http://arago-project.org/cgi-bin/mailman/listinfo/meta-arago
