No SRCREV bump yet. The accepted commit stays on our internal develop branch. It will be externally visible next time we make a tidl-api release (this one missed the PSDK 6.2 window). - Yuan
-----Original Message----- From: Dmytriyenko, Denys Sent: Thursday, January 9, 2020 5:12 PM To: Zhao (Compiler), Yuan Cc: [email protected]; Robey, Caleb Subject: Re: [meta-arago] [PATCH] tidl-api: update BBAI mcbench script On Wed, Jan 08, 2020 at 12:04:12PM -0600, Yuan Zhao wrote: > Signed-off-by: Caleb Robey <[email protected]> > Signed-off-by: Yuan Zhao <[email protected]> > --- > ...p-2-group-layer-use-cases-with-1-dsp.patch | 34 +++++++++++++++++++ > .../recipes-ti/tidl-api/tidl-examples_git.bb | 3 +- > 2 files changed, 36 insertions(+), 1 deletion(-) > create mode 100644 > meta-arago-extras/recipes-ti/tidl-api/files/0002-replace-2-dsp-2-group-layer-use-cases-with-1-dsp.patch > > diff --git > a/meta-arago-extras/recipes-ti/tidl-api/files/0002-replace-2-dsp-2-group-layer-use-cases-with-1-dsp.patch > > b/meta-arago-extras/recipes-ti/tidl-api/files/0002-replace-2-dsp-2-group-layer-use-cases-with-1-dsp.patch > new file mode 100644 > index 00000000..0c78ccf0 > --- /dev/null > +++ > b/meta-arago-extras/recipes-ti/tidl-api/files/0002-replace-2-dsp-2-group-layer-use-cases-with-1-dsp.patch > @@ -0,0 +1,34 @@ > +tidl-api: replace 2 dsp + 2 group layer use cases with 1 dsp > + > + The BBAI only has enough CMEM for 4 EVEs, 1 DSP, and 2 group > + layers. In the case of all of our networks, the difference between > + 1 and 2 dsps is essentially nonexistent. (PLSDK-3189) > + > +Upstream-Status: Accepted Since the patch is marked as "Accepted", shouldn't a simple SRCREV bump be enough? > +Signed-off-by: Caleb Robey <[email protected]> > +Signed-off-by: Yuan Zhao <[email protected]> > +--- > + examples/mcbench/scripts/all_5729.sh | 9 ++++----- > + 1 file changed, 4 insertions(+), 5 deletions(-) > + > +diff --git a/examples/mcbench/scripts/all_5729.sh > b/examples/mcbench/scripts/all_5729.sh > +index defec72..0fee8a1 100755 > +--- a/examples/mcbench/scripts/all_5729.sh > ++++ b/examples/mcbench/scripts/all_5729.sh > +@@ -7,8 +7,7 @@ export TIDL_NETWORK_HEAP_SIZE_DSP=56623104 > + export TIDL_NETWORK_HEAP_SIZE_EVE=67108864 > + export TIDL_NETWORK_HEAP_SIZE_DSP=8388608 > + ./mcbench -g 2 -d 1 -e 4 -c > ../test/testvecs/config/infer/tidl_config_mobileNet1_lg2.txt -f 50 -i > ../test/testvecs/input/preproc_2_224x224_multi.y > +-./mcbench -g 2 -d 2 -e 4 -c > ../test/testvecs/config/infer/tidl_config_mobileNet1_lg2.txt -f 50 -i > ../test/testvecs/input/preproc_2_224x224_multi.y > +-./mcbench -g 2 -d 2 -e 4 -c > ../test/testvecs/config/infer/tidl_config_mobileNet2_lg2.txt -f 50 -i > ../test/testvecs/input/preproc_2_224x224_multi.y > +-./mcbench -g 2 -d 2 -e 4 -c > ../test/testvecs/config/infer/tidl_config_inceptionNetv1_lg2.txt -f 50 -i > ../test/testvecs/input/preproc_0_224x224_multi.y > +-./mcbench -g 2 -d 2 -e 4 -c > ../test/testvecs/config/infer/tidl_config_j11_v2_lg2.txt -f 50 -i > ../test/testvecs/input/preproc_0_224x224_multi.y > +-./mcbench -g 2 -d 2 -e 4 -c > ../test/testvecs/config/infer/tidl_config_j11_v2_dense_lg2.txt -f 50 -i > ../test/testvecs/input/preproc_0_224x224_multi.y > ++./mcbench -g 2 -d 1 -e 4 -c > ../test/testvecs/config/infer/tidl_config_mobileNet2_lg2.txt -f 50 -i > ../test/testvecs/input/preproc_2_224x224_multi.y > ++./mcbench -g 2 -d 1 -e 4 -c > ../test/testvecs/config/infer/tidl_config_inceptionNetv1_lg2.txt -f 50 -i > ../test/testvecs/input/preproc_0_224x224_multi.y > ++./mcbench -g 2 -d 1 -e 4 -c > ../test/testvecs/config/infer/tidl_config_j11_v2_lg2.txt -f 50 -i > ../test/testvecs/input/preproc_0_224x224_multi.y > ++./mcbench -g 2 -d 1 -e 4 -c > ../test/testvecs/config/infer/tidl_config_j11_v2_dense_lg2.txt -f 50 -i > ../test/testvecs/input/preproc_0_224x224_multi.y > +-- > +2.17.1 > + > diff --git a/meta-arago-extras/recipes-ti/tidl-api/tidl-examples_git.bb > b/meta-arago-extras/recipes-ti/tidl-api/tidl-examples_git.bb > index c7016ad5..e5afad1c 100644 > --- a/meta-arago-extras/recipes-ti/tidl-api/tidl-examples_git.bb > +++ b/meta-arago-extras/recipes-ti/tidl-api/tidl-examples_git.bb > @@ -6,7 +6,8 @@ LICENSE = "BSD" > include tidl-api.inc > require recipes-ti/includes/ti-paths.inc > > -PR = "${INC_PR}.0" > +PR = "${INC_PR}.1" > +SRC_URI += > "file://0002-replace-2-dsp-2-group-layer-use-cases-with-1-dsp.patch" > > COMPATIBLE_MACHINE = "dra7xx" > PACKAGE_ARCH = "${MACHINE_ARCH}" > -- > 2.24.1 > > _______________________________________________ > meta-arago mailing list > [email protected] > http://arago-project.org/cgi-bin/mailman/listinfo/meta-arago _______________________________________________ meta-arago mailing list [email protected] http://arago-project.org/cgi-bin/mailman/listinfo/meta-arago
