On 14.04.2014 15:20, Fabio Estevam wrote:
On Mon, Apr 14, 2014 at 9:40 AM, Ingmar Sittl
<[email protected]> wrote:
Starting kernel ...
Uncompressing Linux... done, booting the kernel.
Linux version 3.0.35-4.1.0+yocto+gbdde708 ([email protected]) (gcc version
4.8.1 (GCC) ) #1 SMP PREEMPT Fri Apr 11 12:24:20 CEST 2014
CPU: ARMv7 Processor [412fc09a] revision 10 (ARMv7), cr=10c53c7d
CPU: VIPT nonaliasing data cache, VIPT aliasing instruction cache
Machine: Freescale i.MX 6Quad/DualLite/Solo Sabre-SD Board
Memory policy: ECC disabled, Data cache writealloc
CPU identified as i.MX6Q, silicon rev 1.1
Probably not related to the LVDS issue, but could you try this on a
rev 1.2 instead?
3.0.35 4.1.0 does not officially support rev 1.1.
unfortunately all of our Sabre SDB boards are rev 1.1. If this is no longer
supported, we would stay on LTIB.
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