On 2015-05-11 07:09, Nikolay Dimitrov wrote:
Hi gang,While porting kernel 3.10.53 to an imx6d-based board, I stumbled upon the following issue - my board has a 100 MBit/s RMII PHY which needs 50 MHz reference clock from the SOC, but during the kernel initialization the clock is configured as 125 MHz (observed with a oscilloscope on a test pad). The reference clock is sent from pin GPIO_16 to the PHY. I assume there's no hardware issue with the board, as the old kernel 3.10.17 works fine on the same board. Also U-Boot successfully downloads the 3.10.53 kernel via network, just before observing the fore-mentioned issue. Here are the relevant parts of my DT: &fec { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet_4>; phy-mode = "rmii"; phy-reset-gpios = <&gpio4 5 0>; phy-reset-duration = <1>; status = "okay"; }; &iomuxc { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_hog_1>; enet { pinctrl_enet_4: enetgrp-4 { fsl,pins = < MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0 MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0 MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0 MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 >; }; }; }; Here's a bootlog extract that shows the FEC-related messages: ... libphy: fec_enet_mii_bus: probed fec 2188000.ethernet eth0: registered PHC device 0 ... fec 2188000.ethernet eth0: Freescale FEC PHY driver [SMSC LAN8710/LAN8720] (mii_bus:phy_addr=2188000.ethernet:01, irq =-1) IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready Waiting up to 110 more seconds for network. ... In general, I'm looking at the appropriate way to set the CCM_ANALOG_PLL_ENET.DIV_SELECT to 50 MHz. Thanks in advance for your comments. Regards, Nikolay
Here's how I solved this - I added a "ref-clock" property to my fec node and set it to 50MHz. -- ------------------------------------------------------------ Gary Thomas | Consulting for the MLB Associates | Embedded world ------------------------------------------------------------
>From f7b6e2268d7107e9e260c67644691e64d9432dfd Mon Sep 17 00:00:00 2001 From: Gary Thomas <[email protected]> Date: Wed, 29 Apr 2015 09:19:21 -0600 Subject: [PATCH] Set up and start enet_ref clock - needed by Micrel PHY --- arch/arm/mach-imx/clk-imx6q.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c index 608c9bcf..21dc524 100644 --- a/arch/arm/mach-imx/clk-imx6q.c +++ b/arch/arm/mach-imx/clk-imx6q.c @@ -753,16 +753,18 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) imx_clk_set_rate(clk[pll4_audio_div], 541900800); /* Set [default] enet_ref clock to 125M to supply for RGMII tx_clk */ - clk_set_rate(clk[enet_ref], 125000000); + imx_clk_set_rate(clk[enet_ref], 125000000); np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-fec"); if (np) { u32 clock_frequency; int ret; ret = of_property_read_u32(np, "ref-clock", &clock_frequency); if (ret == 0) { - clk_set_rate(clk[enet_ref], clock_frequency); + imx_clk_set_rate(clk[enet_ref], clock_frequency); } } + // This clock may be needed very early on + imx_clk_prepare_enable(clk[enet_ref]); #ifdef CONFIG_MX6_VPU_352M /* -- 1.9.1
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