On 06/21/2016 20:08, Anders Christensen wrote: > Hi Jonathan, > > Thanks for your reply. > > We have developed our own mainboard based on the Bakersport/Valleyisland > design. > The BIOS is a Coreboot based BIOS version 610 (06/24/15) from Sage > Electronics (which unfortunately is out of business). > The BIOS FSP seems to be a modified version of the GOLD3 release. > My CPU is a D0 stepping and I'm using microcode M0130679907. > By default the USB3 device was disabled in the BIOS, so I have done the > following configuration myself: > > - Enabled the OTG device on the SOC straps (document 514482, section > A.2). > > - Enabled the OTG device in the coreboot devicetree.cb file. > > - Configured an interrupt in the irqroute.h file i.e. added > PCI_DEV_PIRQ_ROUTE(OTG_DEV, D, A, A, A). > > - Enabled the ULPI interface on the GPIO pins (document 526998, > section 7.1). > > - By default the BIOS writes 0x107 to PCI configuration register > 0x04 (PCI_COMMAND). > > - All other registers left unchanged by BIOS. > Our hardware engineers have verified that the ULPI clocks (USB_ULPI_CLK and > USB_ULPI_REFCLK) are running with correct frequencies. > When cable is inserted we can see some additional communication on the ULPI > data and control pins. > I have built our own Yocto 2.0 image with both the default kernel 3.14 as > well as the newer kernel 4.1.15. No change. > I have also tried the Krogoth21/Corei7 BSP with kernel 4.4 as you suggested. > No changes either. > Here is the register dump just after the error occurred (just after loading > the mass storage driver). > By the way, I don't see any changes in register values whether the cable is > inserted or not.
Our engineers are requesting an ACPI table (is there one? I'm not familiar with coreboot) dump along with the kernel configuration. Is the connection a USB uAB or type-C? -- _______________________________________________ meta-intel mailing list [email protected] https://lists.yoctoproject.org/listinfo/meta-intel
