Hi Robert, > -----Original Message----- > From: [email protected] <meta-xilinx- > [email protected]> On Behalf Of Robert P. J. Day > Sent: Thursday, November 21, 2019 12:02 PM > To: [email protected] > Subject: [meta-xilinx] where does FPGA content come from when building > zcu102-zynqmp? > > > i'm about to take a shot at building a QEMU image using meta-xilinx-bsp > layer > for zcu102 and, with what little i know about FPGAs, i was under the > impression > that i *must* supply a .bit or .hdf or .dsa/.xsa file to define the PL part > of the > target. >
Are you using Xilinx release manifest? Whats your layer stack Bitstream is required for FPGA's (which can be present in .hdf/.xsa/.dsa) > must i explicitly provide that, or does the generic zcu102 build have a > generic > FPGA file that will be used if i don't? i just want to get through a build > without > having to become an expert on FPGA stuff, and worry about defining the FPGA > content later. > Generic zcu102 QEMU build will not use anything in PL, hence you will not need anything as such. > thanks. > > rday > > -- > > ================================================================= > ======= > Robert P. J. Day Ottawa, Ontario, CANADA > http://crashcourse.ca > > Twitter: http://twitter.com/rpjday > LinkedIn: http://ca.linkedin.com/in/rpjday > ================================================================= > ======= > -- > _______________________________________________ > meta-xilinx mailing list > [email protected] > https://lists.yoctoproject.org/listinfo/meta-xilinx
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