From: Manjukumar Matha <[email protected]> This recipe will pull in the Xilinx HDMI drivers and associated components, for soft IP, to be built as an out-of-tree modules.
Following drivers will be pulled-in hdmi-rx (v4l2): The HDMI 1.4/2.0 Receiver Subsystem is a feature-rich soft IP incorporating all the necessary logic to properly interface with PHY layers and provide HDMI decoding functionality. The subsystem is a hierarchical IP that bundles a collection of HDMI RX-related IP sub-cores and outputs them as a single IP. The subsystem receives the captured TMDS data from the video PHY layer. It then extracts the video and audio streams from the HDMI stream and converts it to AXI video and audio streams. It includes support for HDCP 1.4 and 2.2 protocols hdmi-tx (drm): HDMI Tx subsystem is a feature-rich soft IP incorporating all the necessary logic to properly interface with xilinx PHY layers and provide HDMI encoding functionality. The subsystem is a hierarchical IP that bundles a collection of HDMI TX-related IP sub-cores and outputs them as a single IP. The subsystem takes incoming video and audio streams and transfers them to an HDMI stream. The stream is then forwarded to the video PHY layer. It includes support for HDCP 1.4 and 2.2 protocols video-phy (phy): Xilinx Video Phy implements the physical layer for enabling the plug-and-play connectivity with HDMI MAC transmit and receive subsystems. This driver is also used as the repository for common files used by hdmi rx and tx drivers including hdcp1.4 and hdcp2.2 software stack si5324 (ccf): Silicon labs clock generator driver specifically targeting the xilinx hdmi use-case. i.e. implemented only functionality required for xilinx hdmi soft IP at this time. dp159 (ccf): SNxDP159 device is a dual mode display port to TMDS retimer supporting DVI 1.0 and HDMI 1.4b and 2.0 output signals. When working as a retimer, the embedded clock data recovery cleans up the input high frequency and random jitter from video source. It also supports TMDS output amplitude adjust and output slew rate control. Signed-off-by: Rohit Consul <[email protected]> Signed-off-by: Shikhar Mishra <[email protected]> Signed-off-by: Sai Hari Chandana Kalluri <[email protected]> Signed-off-by: Manjukumar Matha <[email protected]> --- .../recipes-kernel/hdmi/kernel-module-hdmi_git.bb | 25 ++++++++++++++++++++++ 1 file changed, 25 insertions(+) create mode 100644 meta-xilinx-bsp/recipes-kernel/hdmi/kernel-module-hdmi_git.bb diff --git a/meta-xilinx-bsp/recipes-kernel/hdmi/kernel-module-hdmi_git.bb b/meta-xilinx-bsp/recipes-kernel/hdmi/kernel-module-hdmi_git.bb new file mode 100644 index 0000000..0d93c85 --- /dev/null +++ b/meta-xilinx-bsp/recipes-kernel/hdmi/kernel-module-hdmi_git.bb @@ -0,0 +1,25 @@ +SUMMARY = "Xilinx HDMI Linux Kernel module" +DESCRIPTION = "Out-of-tree HDMI kernel modules provider for MPSoC EG/EV devices" +SECTION = "kernel/modules" +LICENSE = "GPLv2" +LIC_FILES_CHKSUM = "file://LICENSE.md;md5=f230abc77d436836711a1271433a8919" + +XLNX_HDMI_VERSION = "5.4.0" +PV = "${XLNX_HDMI_VERSION}" + +S = "${WORKDIR}/git" + +BRANCH ?= "rel-v2019.2" +REPO ?= "git://github.com/xilinx/hdmi-modules.git;protocol=https" +SRCREV ?= "be354cc3c8889932aabede8cddda0770d77e7843" + +BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != '']}" +SRC_URI = "${REPO};${BRANCHARG}" + +inherit module + +EXTRA_OEMAKE += "O=${STAGING_KERNEL_BUILDDIR}" +COMPATIBLE_MACHINE = "^$" +COMPATIBLE_MACHINE_zynqmp = "zynqmp" + +PACKAGE_ARCH = "${SOC_FAMILY}" -- 2.7.4
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