Hi, I'm facing an issue where my Zynq's XADC internal registers seem to be getting reset during PL reconfiguration.
I'm using the XADC in "Zynq" mode, ie "xlnx,zynq-xadc-1.00.a" and am re-configuring the PL using the fpga_manager interface (echo firmware.bin > /sys/class/fpga_manager/fpga0/firmware). I noticed this as channels 6, 7 and 8 on the ADC would return 0 after a reconfiguration was performed. Littering the XADC driver code with debugging printks it seems as though all of the XADC configuration and sequencing registers (XADC_REG_CONF0/1/2, XADC_REG_SEQ0/1, & XADC_REG_INPUT_MODE0/1) get reset (to 0) after reconfiguration. I was under the impression that because the XADC was a hard macro in the PL it shouldn't be reset through a reconfiguration. But please let me know if I'm wrong about this. Looking through the reconfiguration driver in zynq-fpga.c, it seems as though the PCFG_PROG_B bit is toggled to force a "global reset" of the PL upon reconfiguration. It's not clear from the datasheet whether or not this should effect the XADC, but as it's listed as optional for reconfiguration, I tried removing all writes to it. This seems to sometimes stop the XADC from being reset during reconfiguration but sometimes it still does reset the XADC. I'm a little bit lost of how to proceed with this. I can hack a fix by detecting if the XADC registers are reset in the XADC driver but this is ugly and not really generalizable. I'm happy to keep debugging but any direction of what I should look into would be really appreciated. I'm currently using the Xilinx rel-2018.3 kernel but I tried backporting the latest XADC driver and still had the same issue. Sam
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