On Tue, Feb 9, 2021 at 2:35 PM Peter Smith <[email protected]> wrote:
>
> I’m also very interested in using dunfell (but with the Xilinx flow)
>
> On Tue, 9 Feb 2021 at 12:51, Adrian <[email protected]> wrote:
>>
>> Has anyone ported meta-xilinx to dunfell?
>>
>> Is there any way to use meta-xilinx with newer release than 'zeus'? Is
>> 'master' (according to conf it supports 'dunfell' and 'gatesgarth') stable
>> and could be used?
>>
I am using Yocto gatesgarth release to start a new ZynqMP project with
ZCU102 as my reference board.
My goal is as follows:
As the systems developer, I want my PS configuration + PL design (from
Vivado) source version controlled, and automatically built on CI/CD.
The build artifacts are 1a) bitstream with 1b) an optional matching
.ltx file for ILA's etc, and 2) HDF or XSA files. The latter ones are
the "handoff" (HanDoF) or cross-systems-architecture (XSA) definition
files that are input to their SDK, but preferably also Yocto.
Vivado design -> XSA -> device-tree, PSU firmware source code, PSU
configuration object
ps_init_gpl.c, PSU firmware, PSU configuration object with upstream
U-Boot for the U-Boot SPL (which somewhat replaces FSBL)
ATF, U-Boot, device tree => U-Boot FIT image
I have most of this in place, missing pieces are:
- the PSU configuration object is not generated from the XSA yet.
Maybe with some TCL scripting against the XSCT/HSI this is doable.
- the XSA to device-tree conversion (mostly for IP blocks in the PL,
that are peripherals for the PS). I did not have a look at this yet.
I would like to share Vivado and Yocto projects as public so that we
("the community") share some common ground.
https://github.com/likewise/zcu102-blinky-yocto
https://github.com/likewise/zcu102-blinky
There is some more stuff there, like an example where the ARM can
access the PL DDR through MIG/AXI across HPM LPD.
Also, I have a Vivado 2020.2 Docker image (which works for builds, but
breaks in X11 mode for opening block diagrams).
Regards,
Leon.
p.s. I cannot answer for Xilinx, but would like to share some thoughts:
>> The latest Xilinx releases (v2020.1 and v2020.2) are based on 'zeus' which
>> is more than one year old. There were upgrades in other layers (e.g. Qt)
>> fixing affecting bugs over last year, but they were not backported to
>> 'zeus'. It's surprising and disappointing that the latest Xilinx release
>> v2020 was not based on the latest Yocto release. Why is that?
>>
Í would assume due to the enormous integration and test cycle, they
pick a release when they start a new release train.
I see this as a community effort, Xilinx participating in that
community. And I think Xilinxalthough that might seem a no-brainer,
consider the vendors that do not directly engage in Yocto support for
their silicon (and reprogrammable silicon).
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