Dear meta-xilinx maintainers
The recipe
https://github.com/Xilinx/meta-xilinx/blob/master/meta-xilinx-bsp/recipes-bsp/reference-design/kc705-bitstream_2021.1.bb
fails to build in both master and several previous releases.
I'll refer to gatesgarth branch in the following.
Based on ${PV} (i.e. 2020.2 for gatesgarth branch), the recipe asks for manual
download of xilinx-kc705-v2020.2-final.bsp from Xilinx website.
The SRC_URI[sha256sum] and SRC_URI[md5sum] =
"5c0365a8a26cc27b4419aa1d7dd82351", doesn't match this file, however and the
build thus fails.
Instead, it matches the 2018.3 version:
>md5sum xilinx-kc705-v2018.3-final.bsp
5c0365a8a26cc27b4419aa1d7dd82351 xilinx-kc705-v2018.3-final.bsp
The check-sum parts and some file-naming changes in the
Xilinx-kc705-v2020.2-final.bsp is easy to update in the recipe, and bitbake
core-image-minimal builds without errors then.
Unfortunately, I can't get u-boot output on the console when following the
description in
https://github.com/Xilinx/meta-xilinx/blob/master/meta-xilinx-bsp/README.booting.md
So apparently, the modifications are not ready for a pull-request yet - but
hopefully you can help with the last bits:
Running
xsdb% fpga -f download.bit
provides terminal output on kc705 UART:
FS-BOOT First Stage Bootloader (c) 2013-2014 Xilinx Inc.
Build date: Nov 19 2020 08:48:57
Serial console: Uartlite
FS-BOOT: No existing image in FLASH.
FS-BOOT: Please download the image with JTAG.
The rest of the description in README.booting, especially section "Load U-Boot
(MicroBlaze)", doesn't match what I observe:
Running
xsdb% targets 3 //the original targets -set -filter {name =~ "MicroBlaze*"}
doesn't work because there are both debug and core targets named MicroBlaze,
but 3 is the MicroBlaze core
xsdb% rst
xsdb% dow u-boot.elf
xsdb% con
loads u-boot.elf ok, but does not give any u-boot Console on the UART interface
after con(tinue).
This leads to my question: How is the build system supposed to know the address
map of the hardware configuration in "download.bit" when using the
kc705-bitstream reference design recipe?
I.e., where is the information that should go into the device-tree blob in the
finished system?
Specifically, I can't see how/where the kc705-bitstream_xx.bb recipe tells the
build system where to find e.g. the debug UART, so that u-boot can direct its
output to the right place.
I'm not a Yocto/bitbake expert, so maybe I'm missing something obvious here -
but if you can provide a few hints for the problems, I'd be happy to provide
pull request, do testing on HW etc.
Best regards
Sune Mai
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