On 15-03-16 12:35, Wouter van Gulik wrote:
On 12-03-16 10:54, Sören Brinkmann wrote:
On Fri, 2016-03-11 at 14:04:43 -0800, Moritz Fischer wrote:
Hi Mike,
On Fri, Mar 11, 2016 at 12:49 AM, Mike Looijmans
<[email protected]> wrote:
Hmm, just manually hacking the register values has no effect at all on
the
system. So apparently some other clock is being used as the source.
How can I see (and choose?) which clock is to be used?
It is printed during boot. Some line with 'clocksource' in it, IIRC. I
suspect something in /sys could tell it too.
A bit of digging for "clocksource" in the kernel source code reveals that
the
clocksource can be switched using:
echo ttc_clocksource >
/sys/devices/system/clocksource/clocksource0/current_clocksource
I just wonder now how other platforms handle this, or is the CPU frequency
influencing the HR timer something that's unique to the Zynq?
Most have this properly solved in silicon: use a non changing clock
But not everyone:
http://thread.gmane.org/gmane.linux.documentation/11045/focus=11044
Guess Xilinx just made the same mistake with the Zynq as that other SOC vendor.
The TTC timers should have run from a PLL divider (IO/DDR/ARM) instead of
using the variable cpux1 clock.
The REAL cause of the problem is that the "ttc" clock gives itself a
"rating=200" while the ARM counter gives itself a "rating=300", causing the
evil ARM timer to be preferred over the TTC.
Would it be wise to set the ARM counter clock's rating back to 100 because it
is actually a bad clock and everybody knows it is?
One could use a softcore AxiTimer and fix the whole clock dependency problem.
('any' CPU freq would be possible)
That would only work on systems that can use the logic for that. Some systems
like to re-program the FPGA while running, it's kinda inconvenient if your
clocksource disappears suddenly...
Kind regards,
Mike Looijmans
System Expert
TOPIC Embedded Products
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