On Fri, Dec 23, 2016 at 1:17 AM, Mike Looijmans <[email protected]> wrote: > It's mostly done in hardware. Both CPU's have one or two dedicated lines for > interrupts that can be used in logic. Perfect for systems that only need > one, or for very latency critical tasks. Or for attaching a PL interrupt > controller. > > The SOC interrupt controller, which you're likely using, has a bitmask per > IRQ to specify to what CPU it must be delivered. Probably you're using some > library function to register them, and if you've told it that you're running > on CPU #1, it will set the registers of the IRQ controller such that the > interrupts are routed only to CPU #1.
Yes, I'm using the SOC interrupt controller and am familiar with the interrupt routing register. If the remoteproc devicetree entry is not the thing causing this register to be set, then the only other place I can think of where it might be done is when I target my firmware for CPU1. When I target CPU1, I suppose the BSP generated by the Xilinx SDK sets the routing when I use its library functions to register/enable a particular interrupt. > The PS-PL IRQ controller does not support active-low signals. Simply put an > inverter into the signal line to make them active-high. But my interrupt is not active low, it is rising-edge. The signal just idles high and I want the interrupt to trigger on the rising trailing edge of a negative pulse in the signal. Supporting only active-high and rising-edge interrupts does sort of imply the signal should idle low. Though it doesn't strictly rule out a signal idling high and interrupting on the rising trailing edge of a negative pulse, but something apparently can't handle the interrupt signal idling high even if it's a rising edge trigger. > An interrupt that constantly fires will disrupt the hardware, as it will be > constantly asking for attention. This may 'starve' other interrupts in the > controller. Thank you for all this information! -- _______________________________________________ meta-xilinx mailing list [email protected] https://lists.yoctoproject.org/listinfo/meta-xilinx
