Hi Samuel, On 04/03/19 21:37, Samuel Berezhinskiy wrote: > Hi, > > > > I’ve brought up the board in the sense that I can boot the SPL and make > it into U-Boot as well as being able to come up in Linux. But I seem to > have hit a major wall. After programming the FPGA from U-boot using the > typical command of “fpga loadb 0 <address> <size>” I’m unable to access > any of the AXI devices within the PL from U-boot or Linux, I seem to > just lock up the device, as if the PL is still either powered down or > Isolation is still enabled.
Here are a few more checks that might be helpful. Did you rebuild your pmufw and U-Boot SPL with the pm_cfg_obj.c and psu_init_gpl.c specific for your FPGA design? Try disabling every PL peripheral in your device tree so Linux boots without hanging, then use devmem2 to access a register in your PL devices. Can you read/write registers? Also, are you pairing the right bitstream format with the right U-Boot command? 'fpga load' wants a .bin converted by [0] while (I think) 'fpga loadb' wants the bitstream file produced by Vivado. [0] https://github.com/topic-embedded-products/meta-topic/blob/master/recipes-bsp/fpga/fpga-bit-to-bin/fpga-bit-to-bin.py -- Luca -- _______________________________________________ meta-xilinx mailing list [email protected] https://lists.yoctoproject.org/listinfo/meta-xilinx
