I do not see any reason why not. See (inline) attachments. Apply both. 
And maybe reply to the list if it is working (or not)?

regards,

Bolke


Mark Redding wrote:

>Hi,
>
>would it be possible to share these patches. I've been having similar
>problems with the U530 on generic kernels ( 3.5, 3.6 ). I would love
>patches that work against release if possible.
>
>Regards,
>
>Mark
>
>  
>
>>-----Original Message-----
>>From: [EMAIL PROTECTED] [mailto:[EMAIL PROTECTED] 
>>On Behalf Of Bolke de Bruin
>>Sent: 02 August 2005 09:44
>>To: Federico G. Schwindt
>>Cc: Theo de Raadt; [EMAIL PROTECTED]; [email protected]
>>Subject: Re: Novatel Wireless, Merlin UMTS Modem, NRM6831 - WORKS
>>
>>
>>Federico,
>>
>>The combined patch works. The single patch (eg the second you 
>>sent) did 
>>not by itself. I have attached the dmesg of both. Please note 
>>that the 
>>patches have been applied to 3.6 en the kernel is not Generic as I do 
>>not have a system currently around with 3.7/current and a 
>>cardbus slot. 
>>If still necessary I'll take some time to set it up though.
>>
>>Il try to test a little further to see if I can setup a PPP link.
>>
>>Very kind regards,
>>
>>Bolke
>>OpenBSD 3.6 (NET4511) #5: Tue Aug  2 11:33:51 CEST 2005
>>    [EMAIL PROTECTED]:/usr/src/sys/arch/i386/compile/NET4511
>>cpu0: AMD Am486DX4 W/B or Am5x86 W/B 150 ("AuthenticAMD" 486-class)
>>cpu0: FPU
>>real mem  = 66691072 (65128K)
>>avail mem = 57421824 (56076K)
>>using 839 buffers containing 3436544 bytes (3356K) of memory 
>>mainbus0 (root) bios0 at mainbus0: AT/286+(00) BIOS, date 
>>20/40/11, BIOS32 rev. 0 @ 0xf7840 pcibios0 at bios0: rev 2.0 
>>@ 0xf0000/0x10000
>>pcibios0: pcibios_get_intr_routing - function not supported
>>pcibios0: PCI IRQ Routing information unavailable.
>>pcibios0: PCI bus #1 is the last bus
>>bios0: ROM list: 0xc8000/0xa000
>>cpu0 at mainbus0
>>pci0 at mainbus0 bus 0: configuration mode 1 (no bios)
>>pchb0 at pci0 dev 0 function 0 "AMD ElanSC520 PCI" rev 0x00 
>>cbb0 at pci0 dev 9 function 0 "Texas Instruments PCI1410 
>>CardBus" rev 0x02: irq 10 sis0 at pci0 dev 18 function 0 "NS 
>>DP83815 10/100" rev 0x00: DP83816A, irq 11, address 
>>00:00:24:c2:0a:14 nsphyter0 at sis0 phy 0: DP83815 10/100 
>>integrated, rev. 1 sis1 at pci0 dev 19 function 0 "NS DP83815 
>>10/100" rev 0x00: DP83816A, irq 5, address 00:00:24:c2:0a:15 
>>nsphyter1 at sis1 phy 0: DP83815 10/100 integrated, rev. 1 
>>cardslot0 at cbb0 slot 0 flags 0 cardbus0 at cardslot0: bus 1 
>>device 0 cacheline 0x10, lattimer 0x3f pcmcia0 at cardslot0 
>>isa0 at mainbus0 isadma0 at isa0 pckbc0 at isa0 port 0x60/5 
>>pckbd0 at pckbc0 (kbd slot)
>>pckbc0: using irq 1 for kbd slot
>>wskbd0 at pckbd0: console keyboard
>>wdc0 at isa0 port 0x1f0/8 irq 14
>>wd0 at wdc0 channel 0 drive 0: <SanDisk SDCFB-64>
>>wd0: 1-sector PIO, LBA, 61MB, 125440 sectors
>>wd0(wdc0:0:0): using BIOS timings
>>npx0 at isa0 port 0xf0/16: using exception 16
>>pccom0 at isa0 port 0x3f8/8 irq 4: ns16550a, 16 byte fifo
>>pccom0: console
>>pccom1 at isa0 port 0x2f8/8 irq 3: ns16550a, 16 byte fifo 
>>biomask f7c5 netmask ffe5 ttymask ffe7
>>dkcsum: wd0 matched BIOS disk 80
>>root on wd0a
>>rootdev=0x0 rrootdev=0x300 rawdev=0x302
>>cis mem map d6257000
>>pcmcia0: CIS tuple chain:
>>CISTPL_DEVICE type=null speed=null
>> 01 03 00 00 ff
>>CISTPL_DEVICE_A type=null speed=null
>> 17 03 00 00 ff
>>CISTPL_LONGLINK_MFC 2 attr:4f attr:ce
>> 06 0b 02 00 4f 00 00 00 00 ce 00 00 00
>>CISTPL_MANFID
>> 20 04 a4 00 af 1a
>>CISTPL_VERS_1
>> 15 2f 06 01 4e 6f 76 61 74 65 6c 20 57 69 72 65
>> 6c 65 73 73 00 4d 65 72 6c 69 6e 20 55 4d 54 53
>> 20 4d 6f 64 65 6d 00 4e 52 4d 36 38 33 31 00 00
>> ff
>>CISTPL_END
>> ff
>>cis mem map d6257000
>>CISTPL_LINKTARGET expected, code ff observed
>>cis mem map d6257000
>>CISTPL_FUNCID
>> 21 02 02 01
>>unhandled CISTPL 22
>> 22 04 00 02 0f 7f
>>CISTPL_CONFIG
>> 1a 06 05 05 00 04 63 02
>>CISTPL_CFTABLE_ENTRY
>> 1b 19 c7 01 99 69 55 1d f6 32 2d a3 60 f8 03 07
>> 50 ff ff 48 c1 05 43 4f 4d 31 00
>>CISTPL_CFTABLE_ENTRY
>> 1b 12 0f 98 a3 60 f8 02 07 50 ff ff 48 c1 05 43
>> 4f 4d 32 00
>>CISTPL_CFTABLE_ENTRY
>> 1b 12 17 98 a3 60 e8 03 07 50 ff ff 48 c1 05 43
>> 4f 4d 33 00
>>CISTPL_CFTABLE_ENTRY
>> 1b 12 1f 98 a3 60 e8 02 07 50 ff ff 48 c1 05 43
>> 4f 4d 34 00
>>CISTPL_CFTABLE_ENTRY
>> 1b 0e 27 98 23 50 ff ff 48 c1 05 43 4f 4d 78 00
>>CISTPL_END
>> ff
>>cis mem map d6257000
>>CISTPL_FUNCID
>> 21 02 02 01
>>unhandled CISTPL 22
>> 22 04 00 02 0f 7f
>>CISTPL_CONFIG
>> 1a 06 05 0a 20 04 63 02
>>CISTPL_CFTABLE_ENTRY
>> 1b 19 c7 01 99 69 55 1d f6 32 2d a3 60 f8 02 07
>> 50 ff ff 48 c1 05 43 4f 4d 36 00
>>CISTPL_CFTABLE_ENTRY
>> 1b 12 0f 98 a3 60 f8 03 07 50 ff ff 48 c1 05 43
>> 4f 4d 37 00
>>CISTPL_CFTABLE_ENTRY
>> 1b 12 17 98 a3 60 e8 02 07 50 ff ff 48 c1 05 43
>> 4f 4d 38 00
>>CISTPL_CFTABLE_ENTRY
>> 1b 12 1f 98 a3 60 e8 03 07 50 ff ff 48 c1 05 43
>> 4f 4d 39 00
>>CISTPL_CFTABLE_ENTRY
>> 1b 0e 27 98 23 50 ff ff 48 c1 05 43 4f 4d 79 00
>>CISTPL_END
>> ff
>>pcmcia0: CIS version PC Card Standard 6.1
>>pcmcia0: CIS info: Novatel Wireless, Merlin UMTS Modem, NRM6831,
>>pcmcia0: Manufacturer code 0xa4, product 0x1aaf
>>pcmcia0: function 0: serial port, ccr addr 400 mask 263
>>pcmcia0: function 0, config table entry 7: I/O card; irq mask 
>>ffff; iomask 3, iospace 3f8-3ff; io8 irqpulse audio
>>pcmcia0: function 0, config table entry 15: I/O card; irq 
>>mask ffff; iomask 3, iospace 2f8-2ff; io8 irqpulse audio
>>pcmcia0: function 0, config table entry 23: I/O card; irq 
>>mask ffff; iomask 3, iospace 3e8-3ef; io8 irqpulse audio
>>pcmcia0: function 0, config table entry 31: I/O card; irq 
>>mask ffff; iomask 3, iospace 2e8-2ef; io8 irqpulse audio
>>pcmcia0: function 0, config table entry 39: I/O card; irq 
>>mask ffff; iomask 3, iospace 0-7; io8 irqpulse audio
>>pcmcia0: function 1: serial port, ccr addr 420 mask 263
>>pcmcia0: function 1, config table entry 7: I/O card; irq mask 
>>ffff; iomask 3, iospace 2f8-2ff; io8 irqpulse audio
>>pcmcia0: function 1, config table entry 15: I/O card; irq 
>>mask ffff; iomask 3, iospace 3f8-3ff; io8 irqpulse audio
>>pcmcia0: function 1, config table entry 23: I/O card; irq 
>>mask ffff; iomask 3, iospace 2e8-2ef; io8 irqpulse audio
>>pcmcia0: function 1, config table entry 31: I/O card; irq 
>>mask ffff; iomask 3, iospace 3e8-3ef; io8 irqpulse audio
>>pcmcia0: function 1, config table entry 39: I/O card; irq 
>>mask ffff; iomask 3, iospace 0-7; io8 irqpulse audio pccom2 
>>at pcmcia0 function 0 "Novatel Wireless, Merlin UMTS Modem, 
>>NRM6831" port 0xa3f8/8: ns16550a, 16 byte fifo pccom3 at 
>>pcmcia0 function 1 "Novatel Wireless, Merlin UMTS Modem, 
>>NRM6831" port 0xa2f8/8: ns16550a, 16 byte fifo OpenBSD 3.6 
>>(NET4511) #4: Tue Aug  2 11:24:27 CEST 2005
>>    [EMAIL PROTECTED]:/usr/src/sys/arch/i386/compile/NET4511
>>cpu0: AMD Am486DX4 W/B or Am5x86 W/B 150 ("AuthenticAMD" 486-class)
>>cpu0: FPU
>>real mem  = 66691072 (65128K)
>>avail mem = 57421824 (56076K)
>>using 839 buffers containing 3436544 bytes (3356K) of memory 
>>mainbus0 (root) bios0 at mainbus0: AT/286+(00) BIOS, date 
>>20/40/11, BIOS32 rev. 0 @ 0xf7840 pcibios0 at bios0: rev 2.0 
>>@ 0xf0000/0x10000
>>pcibios0: pcibios_get_intr_routing - function not supported
>>pcibios0: PCI IRQ Routing information unavailable.
>>pcibios0: PCI bus #1 is the last bus
>>bios0: ROM list: 0xc8000/0xa000
>>cpu0 at mainbus0
>>pci0 at mainbus0 bus 0: configuration mode 1 (no bios)
>>pchb0 at pci0 dev 0 function 0 "AMD ElanSC520 PCI" rev 0x00 
>>cbb0 at pci0 dev 9 function 0 "Texas Instruments PCI1410 
>>CardBus" rev 0x02: irq 10 sis0 at pci0 dev 18 function 0 "NS 
>>DP83815 10/100" rev 0x00: DP83816A, irq 11, address 
>>00:00:24:c2:0a:14 nsphyter0 at sis0 phy 0: DP83815 10/100 
>>integrated, rev. 1 sis1 at pci0 dev 19 function 0 "NS DP83815 
>>10/100" rev 0x00: DP83816A, irq 5, address 00:00:24:c2:0a:15 
>>nsphyter1 at sis1 phy 0: DP83815 10/100 integrated, rev. 1 
>>cardslot0 at cbb0 slot 0 flags 0 cardbus0 at cardslot0: bus 1 
>>device 0 cacheline 0x10, lattimer 0x3f pcmcia0 at cardslot0 
>>isa0 at mainbus0 isadma0 at isa0 pckbc0 at isa0 port 0x60/5 
>>pckbd0 at pckbc0 (kbd slot)
>>pckbc0: using irq 1 for kbd slot
>>wskbd0 at pckbd0: console keyboard
>>wdc0 at isa0 port 0x1f0/8 irq 14
>>wd0 at wdc0 channel 0 drive 0: <SanDisk SDCFB-64>
>>wd0: 1-sector PIO, LBA, 61MB, 125440 sectors
>>wd0(wdc0:0:0): using BIOS timings
>>npx0 at isa0 port 0xf0/16: using exception 16
>>pccom0 at isa0 port 0x3f8/8 irq 4: ns16550a, 16 byte fifo
>>pccom0: console
>>pccom1 at isa0 port 0x2f8/8 irq 3: ns16550a, 16 byte fifo 
>>biomask f7c5 netmask ffe5 ttymask ffe7
>>dkcsum: wd0 matched BIOS disk 80
>>root on wd0a
>>rootdev=0x0 rrootdev=0x300 rawdev=0x302
>>cis mem map d6257000
>>pcmcia0: CIS tuple chain:
>>CISTPL_DEVICE type=null speed=null
>> 01 03 00 00 ff
>>CISTPL_DEVICE_A type=null speed=null
>> 17 03 00 00 ff
>>CISTPL_LONGLINK_MFC 2 attr:4f attr:ce
>> 06 0b 02 00 4f 00 00 00 00 ce 00 00 00
>>CISTPL_MANFID
>> 20 04 a4 00 af 1a
>>CISTPL_VERS_1
>> 15 2f 06 01 4e 6f 76 61 74 65 6c 20 57 69 72 65
>> 6c 65 73 73 00 4d 65 72 6c 69 6e 20 55 4d 54 53
>> 20 4d 6f 64 65 6d 00 4e 52 4d 36 38 33 31 00 00
>> ff
>>CISTPL_END
>> ff
>>cis mem map d6257000
>>CISTPL_LINKTARGET expected, code ff observed
>>cis mem map d6257000
>>CISTPL_FUNCID
>> 21 02 02 01
>>unhandled CISTPL 22
>> 22 04 00 02 0f 7f
>>CISTPL_CONFIG
>> 1a 06 05 05 00 04 63 02
>>CISTPL_CFTABLE_ENTRY
>> 1b 19 c7 01 99 69 55 1d f6 32 2d a3 60 f8 03 07
>> 50 ff ff 48 c1 05 43 4f 4d 31 00
>>CISTPL_CFTABLE_ENTRY
>> 1b 12 0f 98 a3 60 f8 02 07 50 ff ff 48 c1 05 43
>> 4f 4d 32 00
>>CISTPL_CFTABLE_ENTRY
>> 1b 12 17 98 a3 60 e8 03 07 50 ff ff 48 c1 05 43
>> 4f 4d 33 00
>>CISTPL_CFTABLE_ENTRY
>> 1b 12 1f 98 a3 60 e8 02 07 50 ff ff 48 c1 05 43
>> 4f 4d 34 00
>>CISTPL_CFTABLE_ENTRY
>> 1b 0e 27 98 23 50 ff ff 48 c1 05 43 4f 4d 78 00
>>CISTPL_END
>> ff
>>cis mem map d6257000
>>CISTPL_FUNCID
>> 21 02 02 01
>>unhandled CISTPL 22
>> 22 04 00 02 0f 7f
>>CISTPL_CONFIG
>> 1a 06 05 0a 20 04 63 02
>>CISTPL_CFTABLE_ENTRY
>> 1b 19 c7 01 99 69 55 1d f6 32 2d a3 60 f8 02 07
>> 50 ff ff 48 c1 05 43 4f 4d 36 00
>>CISTPL_CFTABLE_ENTRY
>> 1b 12 0f 98 a3 60 f8 03 07 50 ff ff 48 c1 05 43
>> 4f 4d 37 00
>>CISTPL_CFTABLE_ENTRY
>> 1b 12 17 98 a3 60 e8 02 07 50 ff ff 48 c1 05 43
>> 4f 4d 38 00
>>CISTPL_CFTABLE_ENTRY
>> 1b 12 1f 98 a3 60 e8 03 07 50 ff ff 48 c1 05 43
>> 4f 4d 39 00
>>CISTPL_CFTABLE_ENTRY
>> 1b 0e 27 98 23 50 ff ff 48 c1 05 43 4f 4d 79 00
>>CISTPL_END
>> ff
>>pcmcia0: CIS version PC Card Standard 6.1
>>pcmcia0: CIS info: Novatel Wireless, Merlin UMTS Modem, NRM6831,
>>pcmcia0: Manufacturer code 0xa4, product 0x1aaf
>>pcmcia0: function 0: serial port, ccr addr 400 mask 263
>>pcmcia0: function 0, config table entry 7: I/O card; irq mask 
>>ffff; iomask 3, iospace 3f8-3ff; io8 irqpulse audio
>>pcmcia0: function 0, config table entry 15: I/O card; irq 
>>mask ffff; iomask 3, iospace 2f8-2ff; io8 irqpulse audio
>>pcmcia0: function 0, config table entry 23: I/O card; irq 
>>mask ffff; iomask 3, iospace 3e8-3ef; io8 irqpulse audio
>>pcmcia0: function 0, config table entry 31: I/O card; irq 
>>mask ffff; iomask 3, iospace 2e8-2ef; io8 irqpulse audio
>>pcmcia0: function 0, config table entry 39: I/O card; irq 
>>mask ffff; iomask 3, iospace 0-7; io8 irqpulse audio
>>pcmcia0: function 1: serial port, ccr addr 420 mask 263
>>pcmcia0: function 1, config table entry 7: I/O card; irq mask 
>>ffff; iomask 3, iospace 2f8-2ff; io8 irqpulse audio
>>pcmcia0: function 1, config table entry 15: I/O card; irq 
>>mask ffff; iomask 3, iospace 3f8-3ff; io8 irqpulse audio
>>pcmcia0: function 1, config table entry 23: I/O card; irq 
>>mask ffff; iomask 3, iospace 2e8-2ef; io8 irqpulse audio
>>pcmcia0: function 1, config table entry 31: I/O card; irq 
>>mask ffff; iomask 3, iospace 3e8-3ef; io8 irqpulse audio
>>pcmcia0: function 1, config table entry 39: I/O card; irq 
>>mask ffff; iomask 3, iospace 0-7; io8 irqpulse audio pccom2 
>>at pcmcia0 function 0 "Novatel Wireless, Merlin UMTS Modem, 
>>NRM6831" port 0xa3f8/8: ns16550a, 16 byte fifo pccom3 at 
>>pcmcia0 function 1 "Novatel Wireless, Merlin UMTS Modem, 
>>NRM6831" port 0xa2f8/8: ns16550a, 16 byte fifo
Index: sys/dev/pcmcia/pcmcia.c
===================================================================
RCS file: /cvs/src/sys/dev/pcmcia/pcmcia.c,v
retrieving revision 1.34
diff -u -p -r1.34 pcmcia.c
--- sys/dev/pcmcia/pcmcia.c     2005/01/27 17:03:23     1.34
+++ sys/dev/pcmcia/pcmcia.c     2005/08/01 23:07:45
@@ -512,22 +512,16 @@ pcmcia_function_enable(pf)
        pcmcia_ccr_write(pf, PCMCIA_CCR_SOCKETCOPY, 0);
        
        if (pcmcia_mfc(pf->sc)) {
-               long tmp, iosize;
-
-               tmp = pf->pf_mfc_iomax - pf->pf_mfc_iobase;
-               /* round up to nearest (2^n)-1 */
-               for (iosize = 1; iosize < tmp; iosize <<= 1)
-                       ;
-               iosize--;
-
                pcmcia_ccr_write(pf, PCMCIA_CCR_IOBASE0,
-                                pf->pf_mfc_iobase & 0xff);
+                                (pf->pf_mfc_iobase >>  0) & 0xff);
                pcmcia_ccr_write(pf, PCMCIA_CCR_IOBASE1,
-                                (pf->pf_mfc_iobase >> 8) & 0xff);
-               pcmcia_ccr_write(pf, PCMCIA_CCR_IOBASE2, 0);
-               pcmcia_ccr_write(pf, PCMCIA_CCR_IOBASE3, 0);
-
-               pcmcia_ccr_write(pf, PCMCIA_CCR_IOSIZE, iosize);
+                                (pf->pf_mfc_iobase >>  8) & 0xff);
+               pcmcia_ccr_write(pf, PCMCIA_CCR_IOBASE2, 
+                                (pf->pf_mfc_iobase >> 16) & 0xff);
+               pcmcia_ccr_write(pf, PCMCIA_CCR_IOBASE3,
+                                (pf->pf_mfc_iobase >> 24) & 0xff);
+               pcmcia_ccr_write(pf, PCMCIA_CCR_IOSIZE,
+                                pf->pf_mfc_iomax - pf->pf_mfc_iobase);
        }
 
 #ifdef PCMCIADEBUG
@@ -644,33 +638,29 @@ pcmcia_io_map(pf, width, offset, size, p
         */
 
        if (pcmcia_mfc(pf->sc)) {
-               long tmp, iosize;
+               bus_addr_t iobase = pcihp->addr;
+               bus_addr_t iomax = pcihp->addr + pcihp->size - 1;
 
                if (pf->pf_mfc_iomax == 0) {
-                       pf->pf_mfc_iobase = pcihp->addr + offset;
-                       pf->pf_mfc_iomax = pf->pf_mfc_iobase + size;
+                       pf->pf_mfc_iobase = iobase;
+                       pf->pf_mfc_iomax = iomax;
                } else {
-                       /* This makes the assumption that nothing overlaps. */
-                       if (pf->pf_mfc_iobase > pcihp->addr + offset)
-                               pf->pf_mfc_iobase = pcihp->addr + offset;
-                       if (pf->pf_mfc_iomax < pcihp->addr + offset + size)
-                               pf->pf_mfc_iomax = pcihp->addr + offset + size;
+                       if (iobase < pf->pf_mfc_iobase)
+                               pf->pf_mfc_iobase = iobase;
+                       if (iomax > pf->pf_mfc_iomax)
+                               pf->pf_mfc_iomax = iomax;
                }
 
-               tmp = pf->pf_mfc_iomax - pf->pf_mfc_iobase;
-               /* round up to nearest (2^n)-1 */
-               for (iosize = 1; iosize >= tmp; iosize <<= 1)
-                       ;
-               iosize--;
-
                pcmcia_ccr_write(pf, PCMCIA_CCR_IOBASE0,
-                                pf->pf_mfc_iobase & 0xff);
+                                (pf->pf_mfc_iobase >>  0) & 0xff);
                pcmcia_ccr_write(pf, PCMCIA_CCR_IOBASE1,
-                                (pf->pf_mfc_iobase >> 8) & 0xff);
-               pcmcia_ccr_write(pf, PCMCIA_CCR_IOBASE2, 0);
-               pcmcia_ccr_write(pf, PCMCIA_CCR_IOBASE3, 0);
-
-               pcmcia_ccr_write(pf, PCMCIA_CCR_IOSIZE, iosize);
+                                (pf->pf_mfc_iobase >>  8) & 0xff);
+               pcmcia_ccr_write(pf, PCMCIA_CCR_IOBASE2,
+                                (pf->pf_mfc_iobase >> 16) & 0xff);
+               pcmcia_ccr_write(pf, PCMCIA_CCR_IOBASE3,
+                                (pf->pf_mfc_iobase >> 24) & 0xff);
+               pcmcia_ccr_write(pf, PCMCIA_CCR_IOSIZE,
+                                pf->pf_mfc_iomax - pf->pf_mfc_iobase);
 
                reg = pcmcia_ccr_read(pf, PCMCIA_CCR_OPTION);
                reg |= PCMCIA_CCR_OPTION_ADDR_DECODE;
Index: sys/dev/pcmcia/pcmciavar.h
===================================================================
RCS file: /cvs/src/sys/dev/pcmcia/pcmciavar.h,v
retrieving revision 1.18
diff -u -p -r1.18 pcmciavar.h
--- sys/dev/pcmcia/pcmciavar.h  2005/01/27 17:03:23     1.18
+++ sys/dev/pcmcia/pcmciavar.h  2005/08/01 23:07:45
@@ -124,10 +124,10 @@ struct pcmcia_function {
 #define        pf_ccrh         pf_pcmh.memh
 #define        pf_ccr_mhandle  pf_pcmh.mhandle
 #define        pf_ccr_realsize pf_pcmh.realsize
-       bus_addr_t      pf_ccr_offset;
+       bus_size_t      pf_ccr_offset;
        int             pf_ccr_window;
-       long            pf_mfc_iobase;
-       long            pf_mfc_iomax;
+       bus_addr_t      pf_mfc_iobase;
+       bus_addr_t      pf_mfc_iomax;
        int             (*ih_fct)(void *);
        void            *ih_arg;
        int             ih_ipl;
Index: sys/dev/pci/pccbb.c
===================================================================
RCS file: /cvs/src/sys/dev/pci/pccbb.c,v
retrieving revision 1.35
diff -u -p -r1.35 pccbb.c
--- sys/dev/pci/pccbb.c 2005/01/27 17:03:23     1.35
+++ sys/dev/pci/pccbb.c 2005/08/01 23:54:40
@@ -1958,6 +1958,7 @@ pccbb_pcmcia_io_alloc(pch, start, size, 
        int flags = 0;
        bus_space_tag_t iot;
        bus_space_handle_t ioh;
+       bus_addr_t mask;
 #if rbus
        rbus_tag_t rb;
 #endif
@@ -1965,6 +1966,34 @@ pccbb_pcmcia_io_alloc(pch, start, size, 
                align = size;          /* XXX: funny??? */
        }
 
+       if (start != 0) {
+               /* XXX: assume all card decode lower 10 bits by its hardware */
+               mask = 0x3ff;
+               /* enforce to use only masked address */
+               start &= mask;
+       } else {
+               /*
+                * calculate mask:
+                *  1. get the most significant bit of size (call it msb).
+                *  2. compare msb with the value of size.
+                *  3. if size is larger, shift msb left once.
+                *  4. obtain mask value to decrement msb.
+                */
+               bus_size_t size_tmp = size;     
+               int shifts = 0;
+
+               mask = 1;
+               while (size_tmp) {
+                       ++shifts;
+                       size_tmp >>= 1;
+               }
+               mask = (1 << shifts);
+               if (mask < size) {
+                       mask <<= 1;
+               }
+               mask--;
+       }
+
        /*
         * Allocate some arbitrary I/O space.
         */
@@ -1973,8 +2002,7 @@ pccbb_pcmcia_io_alloc(pch, start, size, 
 
 #if rbus
        rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot;
-       /* XXX: I assume all card decode lower 10 bits by its hardware */
-       if (rbus_space_alloc(rb, start, size, 0x3ff, align, 0, &ioaddr, &ioh)) {
+       if (rbus_space_alloc(rb, start, size, mask, align, 0, &ioaddr, &ioh)) {
                return 1;
        }
 #else
@@ -1983,7 +2011,7 @@ pccbb_pcmcia_io_alloc(pch, start, size, 
                if (bus_space_map(iot, start, size, 0, &ioh)) {
                        return 1;
                }
-               DPRINTF(("pccbb_pcmcia_io_alloc map port %lx+%lx\n",
+               DPRINTF(("pccbb_pcmcia_io_alloc map port 0x%lx+0x%lx\n",
                    (u_long) ioaddr, (u_long) size));
        } else {
                flags |= PCMCIA_IO_ALLOCATED;

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