On Fri, 7 Oct 2005 09:08, you wrote:
> I wondered that as well, but there appear to be lots (so it appears from
> other postings I found using google) of 4801s in use with OpenBSD, doing
> essentially the same thing as myself (Soekris w/ carp/pf/pfsynch). Yet,
> AFAICT, I'm the only one who's posted about this symptom. Since there are
> lots of people who do what I do, and if the problem were indeed that the
> 4801 processor is too wimpy, then wouldn't there be more problems like mine
> mentioned in the lists? And I'm running into high interrupts with only
> about 4Mbs throughput while others have claimed much higher values.
>
> Before I used this firewall that I have now, I used m0n0wall on FreeBSD. I
> chose OpenBSD over m0n0wall/FreeBSD due to m0n0wall state table limitations
> and lack of mature redundance features. But the m0n0wall handled this much
> traffic, and more, with a relatively low interrupt mode. As widely as
> OpenBSD is used on Soekris for firewalling compared to m0n0wall/FreeBSD
> with relatively few problems, I'm still not quite ready to decide that I
> haven't gotten myself a setup flaw somewhere. Just can't figure out where
> it could be.
>
>
You'll find a few of us are running the interrupt holdoff patch, which IIRC,
comes from the FreeBSD tree via [EMAIL PROTECTED] (See below).
Patch trades off timeliness of response for reduced interrupts.
Index: src/sys/dev/pci/if_sis.c
===================================================================
RCS file: /cvs/src/sys/dev/pci/if_sis.c,v
retrieving revision 1.46
diff -u -r1.46 if_sis.c
--- src/sys/dev/pci/if_sis.c 27 May 2005 04:52:24 -0000 1.46
+++ src/sys/dev/pci/if_sis.c 7 Jun 2005 07:14:37 -0000
@@ -1692,6 +1692,10 @@
sis_stop(sc);
sc->sis_stopped = 0;
+ /* Configure interrupt holdoff register. */
+ if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr == NS_SRR_16A)
+ CSR_WRITE_4(sc, NS_IHR, NS_IHR_VALUE);
+
mii = &sc->sc_mii;
/* Set MAC address */
Index: src/sys/dev/pci/if_sisreg.h
===================================================================
RCS file: /cvs/src/sys/dev/pci/if_sisreg.h,v
retrieving revision 1.21
diff -u -r1.21 if_sisreg.h
--- src/sys/dev/pci/if_sisreg.h 22 May 2005 05:40:52 -0000 1.21
+++ src/sys/dev/pci/if_sisreg.h 7 Jun 2005 07:14:38 -0000
@@ -208,6 +208,20 @@
SIS_IMR_RX_IDLE|\
SIS_IMR_SYSERR)
+/* Interrupt Holdoff Register */
+#define NS_IHR_HOLDCTL 0x00000100
+
+/*
+ * Interrupt holdoff value for NS DP8316. We can have the chip
+ * delay interrupt delivery for a certain period. Units are in
+ * 100us, and the default is 100us holdoff.
+ */
+#ifndef NS_IHR_DELAY
+#define NS_IHR_DELAY 2
+#endif
+
+#define NS_IHR_VALUE (NS_IHR_HOLDCTL|NS_IHR_DELAY)
+
#define SIS_IER_INTRENB 0x00000001
#define SIS_PHYCTL_ACCESS 0x00000010
--
Craig
