* J.C. Roberts <[EMAIL PROTECTED]> [2005-11-09 16:50]: > On Wed, 9 Nov 2005 14:34:27 +0100, Henning Brauer > <[EMAIL PROTECTED]> wrote: > >* J.C. Roberts <[EMAIL PROTECTED]> [2005-11-08 10:26]: > >> Now think to yourself on this one. You've got 60 tunnels that must be > >> serviced by the processor. A single threaded processor with limited > >> cache and task switching (i.e. Celeron) is the wrong choice if not the > >> worst choice you could make. The fake multi-core Intel stuff called > >> "Hyper Threading" is a small step in the right direction. Next up would > >> be real multi-core processors, and lastly, your best choice is having > >> multiple multi-core processors. > >no. > >there is no benefit from SMP in this case. > None at all? -Hmmm... sounds suspicious. > > I assume Otto is correct about the IPSec implementation being in kernel > and not benefitting directly from SMP, yet depending on what *else* is > running on the box, smp could still provide some indirect benefit by off > loading the other stuff to a second processor/core.
in theory, yes. and then there's extra syncronization and locking cost in the SMP case. -- BS Web Services, http://www.bsws.de/ OpenBSD-based Webhosting, Mail Services, Managed Servers, ... Unix is very simple, but it takes a genius to understand the simplicity. (Dennis Ritchie)
