On Thu, Oct 10, 2013 at 05:48:43PM -0400, RD Thrush wrote:
> I noticed some anomalies in the dmesg on this new system.
>
> 1. error: [drm:pid0:i915_write32] *ERROR* Unknown unclaimed register before
> writing to 100000
>
> 2. dhclient doesn't work with the onboard nic (possibly since the lladdr is
> 0:0:0:0:0:0.
There is no support for Realtek 8168G/8111G devices, here is a diff which
apparently lacks some critical part required to make it work
as it didn't work for the last person who tried it.
Index: re.c
===================================================================
RCS file: /cvs/src/sys/dev/ic/re.c,v
retrieving revision 1.144
diff -u -p -r1.144 re.c
--- re.c 5 Oct 2013 22:59:57 -0000 1.144
+++ re.c 9 Oct 2013 01:21:41 -0000
@@ -223,6 +223,8 @@ static const struct re_revision {
{ RL_HWREV_8101, "RTL8101" },
{ RL_HWREV_8101E, "RTL8101E" },
{ RL_HWREV_8102E, "RTL8102E" },
+ { RL_HWREV_8106E, "RTL8106E" },
+ { RL_HWREV_8106E_SPIN1, "RTL8106E" },
{ RL_HWREV_8401E, "RTL8401E" },
{ RL_HWREV_8402, "RTL8402" },
{ RL_HWREV_8411, "RTL8411" },
@@ -238,6 +240,10 @@ static const struct re_revision {
{ RL_HWREV_8168C_SPIN2, "RTL8168C/8111C" },
{ RL_HWREV_8168CP, "RTL8168CP/8111CP" },
{ RL_HWREV_8168F, "RTL8168F/8111F" },
+ { RL_HWREV_8168G, "RTL8168G/8111G" },
+ { RL_HWREV_8168G_SPIN1, "RTL8168G/8111G" },
+ { RL_HWREV_8168G_SPIN2, "RTL8168G/8111G" },
+ { RL_HWREV_8168G_SPIN4, "RTL8168G/8111G" },
{ RL_HWREV_8105E, "RTL8105E" },
{ RL_HWREV_8105E_SPIN1, "RTL8105E" },
{ RL_HWREV_8168D, "RTL8168D/8111D" },
@@ -846,6 +852,8 @@ re_attach(struct rl_softc *sc, const cha
case RL_HWREV_8402:
case RL_HWREV_8105E:
case RL_HWREV_8105E_SPIN1:
+ case RL_HWREV_8106E:
+ case RL_HWREV_8106E_SPIN1:
sc->rl_flags |= RL_FLAG_INVMAR | RL_FLAG_PHYWAKE |
RL_FLAG_PHYWAKE_PM | RL_FLAG_PAR | RL_FLAG_DESCV2 |
RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD |
@@ -892,6 +900,15 @@ re_attach(struct rl_softc *sc, const cha
RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT |
RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD | RL_FLAG_NOJUMBO;
break;
+ case RL_HWREV_8168G:
+ case RL_HWREV_8168G_SPIN1:
+ case RL_HWREV_8168G_SPIN2:
+ case RL_HWREV_8168G_SPIN4:
+ sc->rl_flags |= RL_FLAG_INVMAR | RL_FLAG_PHYWAKE |
+ RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT |
+ RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD | RL_FLAG_NOJUMBO |
+ RL_FLAG_EARLYOFF;
+ break;
case RL_HWREV_8169_8110SB:
case RL_HWREV_8169_8110SBL:
case RL_HWREV_8169_8110SCd:
@@ -1974,6 +1991,7 @@ re_init(struct ifnet *ifp)
{
struct rl_softc *sc = ifp->if_softc;
u_int16_t cfg;
+ uint32_t rxcfg;
int s;
union {
u_int32_t align_dummy;
@@ -2058,7 +2076,10 @@ re_init(struct ifnet *ifp)
CSR_WRITE_1(sc, RL_EARLY_TX_THRESH, 16);
- CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG);
+ rxcfg = RL_RXCFG_CONFIG;
+ if (sc->rl_flags & RL_FLAG_EARLYOFF)
+ rxcfg |= RL_RXCFG_EARLYOFF;
+ CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
/* Program promiscuous mode and multicast filters. */
re_iff(sc);
Index: rtl81x9reg.h
===================================================================
RCS file: /cvs/src/sys/dev/ic/rtl81x9reg.h,v
retrieving revision 1.76
diff -u -p -r1.76 rtl81x9reg.h
--- rtl81x9reg.h 17 Mar 2013 20:47:23 -0000 1.76
+++ rtl81x9reg.h 3 Aug 2013 13:54:57 -0000
@@ -186,8 +186,14 @@
#define RL_HWREV_8105E 0x40800000
#define RL_HWREV_8105E_SPIN1 0x40C00000
#define RL_HWREV_8402 0x44000000
+#define RL_HWREV_8106E 0x44800000
+#define RL_HWREV_8106E_SPIN1 0x44900000
#define RL_HWREV_8168F 0x48000000
#define RL_HWREV_8411 0x48800000
+#define RL_HWREV_8168G 0x4c000000
+#define RL_HWREV_8168G_SPIN1 0x4c100000
+#define RL_HWREV_8168G_SPIN2 0x50900000
+#define RL_HWREV_8168G_SPIN4 0x5c800000
#define RL_HWREV_8139 0x60000000
#define RL_HWREV_8139A 0x70000000
#define RL_HWREV_8139AG 0x70800000
@@ -277,6 +283,7 @@
#define RL_RXCFG_RX_RUNT 0x00000010
#define RL_RXCFG_RX_ERRPKT 0x00000020
#define RL_RXCFG_WRAP 0x00000080
+#define RL_RXCFG_EARLYOFF 0x00000100
#define RL_RXCFG_MAXDMA 0x00000700
#define RL_RXCFG_BURSZ 0x00001800
#define RL_RXCFG_FIFOTHRESH 0x0000E000
@@ -847,6 +854,7 @@ struct rl_softc {
#define RL_FLAG_AUTOPAD 0x00004000
#define RL_FLAG_LINK 0x00008000
#define RL_FLAG_PHYWAKE_PM 0x00010000
+#define RL_FLAG_EARLYOFF 0x00020000
u_int16_t rl_intrs;
u_int16_t rl_tx_ack;
