On Sun, Nov 02, 2014 at 08:11:51AM +0100, [email protected] wrote: > I have tested the driver on both openbsd 5.5 and 5.6, not on current. > > > OpenBSD 5.6-stable (GENERIC.MP) #6: Sat Nov 1 14:02:01 CET 2014 > [email protected]:/usr/src/sys/arch/amd64/compile/GENERIC.MP > real mem = 4157509632 (3964MB) > avail mem = 4038041600 (3850MB) > mpath0 at root > scsibus0 at mpath0: 256 targets > mainbus0 at root > bios0 at mainbus0: SMBIOS rev. 2.7 @ 0xebdb0 (22 entries) > bios0: vendor American Megatrends Inc. version "S400CA.207" date 12/27/2012 > bios0: ASUSTeK COMPUTER INC. S400CA > > ... > > alc0 at pci3 dev 0 function 0 "Attansic Technology AR8161" rev 0x10 > > > Diffs are appended. > I have tested the driver on hw L2C and AR8161. > When looking at the diff I saw that there are some obsolete predefinition > left in the code. They have not generated any warnings, but might be > confusing for a reviewer. > I read that the freebsd driver have som problems at long cable length. If you > have access to an artificial ethernet cable this could be a subject for > testing. >
Hi, Thanks for your work. 'if_alc.c.diff' didn't apply correctly because of some formatting differences - mostly spaces and TABs. I spend few hours to correct it and now it apply against if_alc.c revision 1.27. 'if_alcreg.h' is not a diff, it's if_alcreg.h revision 1.4. I used if_alcreg.h from sourceforge.net. Both diffs are appended inline so other people could test. As a result my "Attansic Technology AR8161" works as it should. Best wishes, Atanas Index: if_alc.c =================================================================== RCS file: /home/vlado/cvsync/cvsroot/src/sys/dev/pci/if_alc.c,v retrieving revision 1.27 diff -u -p -r1.27 if_alc.c --- if_alc.c 22 Jul 2014 13:12:11 -0000 1.27 +++ if_alc.c 2 Nov 2014 15:11:59 -0000 @@ -1,5 +1,10 @@ + +/* $OpenBSD: if_alc.c,v 1.26 2013/12/28 03:34:53 deraadt Exp $ */ +/*- patched by oht to fit with the AR816X_FAMILY*/ + /* $OpenBSD: if_alc.c,v 1.27 2014/07/22 13:12:11 mpi Exp $ */ /*- +>>>>>>> 1.27 * Copyright (c) 2009, Pyun YongHyeon <[email protected]> * All rights reserved. * @@ -26,7 +31,7 @@ * SUCH DAMAGE. */ -/* Driver for Atheros AR8131/AR8132 PCIe Ethernet. */ +/* Driver for Atheros AR8131/AR8132 AR8161/AR8162 AR8171/AR8172 PCIe Ethernet. */ #include "bpfilter.h" #include "vlan.h" @@ -84,12 +89,17 @@ void alc_watchdog(struct ifnet *); int alc_mediachange(struct ifnet *); void alc_mediastatus(struct ifnet *, struct ifmediareq *); -void alc_aspm(struct alc_softc *, int); +void alc_aspm(struct alc_softc *, int, int); +void alc_aspm_813x(struct alc_softc *, int); +void alc_aspm_816x(struct alc_softc *, int); void alc_disable_l0s_l1(struct alc_softc *); int alc_dma_alloc(struct alc_softc *); void alc_dma_free(struct alc_softc *); int alc_encap(struct alc_softc *, struct mbuf **); void alc_get_macaddr(struct alc_softc *); + void alc_get_macaddr_813x(struct alc_softc *); + void alc_get_macaddr_816x(struct alc_softc *); + void alc_get_macaddr_par(struct alc_softc *); void alc_init_cmb(struct alc_softc *); void alc_init_rr_ring(struct alc_softc *); int alc_init_rx_ring(struct alc_softc *); @@ -97,9 +107,26 @@ void alc_init_smb(struct alc_softc *); void alc_init_tx_ring(struct alc_softc *); int alc_intr(void *); void alc_mac_config(struct alc_softc *); + uint32_t alc_mii_readreg_813x(struct alc_softc *, int, int); + uint32_t alc_mii_readreg_816x(struct alc_softc *, int, int); + uint32_t alc_mii_writereg_813x(struct alc_softc *, int, int, int); + uint32_t alc_mii_writereg_816x(struct alc_softc *, int, int, int); + void alc_dsp_fixup(struct alc_softc *, int); + int alc_miibus_readreg(struct device *, int, int); void alc_miibus_statchg(struct device *); +int alc_miibus_writeregr(struct device *, int, int, int); void alc_miibus_writereg(struct device *, int, int, int); + uint32_t alc_miidbg_readreg(struct alc_softc *, int); + uint32_t alc_miidbg_writereg(struct alc_softc *, int, int); + uint32_t alc_miiext_readreg(struct alc_softc *, int, int); + uint32_t alc_miiext_writereg(struct alc_softc *, int, int, int); + //int alc_mediachange_locked(struct alc_softc *); + void alc_phy_reset_813x(struct alc_softc *); + void alc_phy_reset_816x(struct alc_softc *); + void alc_setwol_813x(struct alc_softc *); + void alc_setwol_816x(struct alc_softc *); + int alc_newbuf(struct alc_softc *, struct alc_rxdesc *); void alc_phy_down(struct alc_softc *); void alc_phy_reset(struct alc_softc *); @@ -116,6 +143,18 @@ void alc_stop_mac(struct alc_softc *); void alc_stop_queue(struct alc_softc *); void alc_tick(void *); void alc_txeof(struct alc_softc *); +void alc_init_pcie(struct alc_softc *, int); +void alc_config_msi(struct alc_softc *); + +int alc_dma_alloc(struct alc_softc *); +void alc_dma_free(struct alc_softc *); +int alc_encap(struct alc_softc *, struct mbuf **); +void alc_osc_reset(struct alc_softc *); + + +int device_print_prettyname(struct alc_softc *); +int device_printf(struct alc_softc *, const char * , ...); + uint32_t alc_dma_burst[] = { 128, 256, 512, 1024, 2048, 4096, 0 }; @@ -125,11 +164,16 @@ const struct pci_matchid alc_devices[] = { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_L1D }, { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_L1D_1 }, { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_L2C_1 }, - { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_L2C_2 } + { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_L2C_2 }, + { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8161 }, + { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8162 }, + { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8171 }, + { PCI_VENDOR_ATTANSIC, PCI_PRODUCT_ATTANSIC_AR8172 } + }; struct cfattach alc_ca = { - sizeof (struct alc_softc), alc_match, alc_attach, NULL, + sizeof (struct alc_softc), alc_match, alc_attach, alc_detach, alc_activate }; @@ -138,6 +182,32 @@ struct cfdriver alc_cd = { }; int alcdebug = 0; + +int + device_print_prettyname(struct alc_softc *sc) + { + const char *name =sc->sc_dev.dv_xname; + + if (name == NULL) + return (printf("unknown: ")); + return (printf("%s: ", name)); + } + +int + device_printf(struct alc_softc *sc, const char * fmt, ...) +{ + va_list ap; + int retval; + if ( alcdebug == 0) + return 0; + + retval = device_print_prettyname(sc); + va_start(ap, fmt); + retval += vprintf(fmt, ap); + va_end(ap); + return (retval); +} + #define DPRINTF(x) do { if (alcdebug) printf x; } while (0) #define ALC_CSUM_FEATURES (M_TCP_CSUM_OUT | M_UDP_CSUM_OUT) @@ -146,9 +216,21 @@ int alc_miibus_readreg(struct device *dev, int phy, int reg) { struct alc_softc *sc = (struct alc_softc *)dev; + uint32_t v = 0; + if (phy != sc->alc_phyaddr) + return (0); + + if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) + v = alc_mii_readreg_816x(sc, phy, reg); + else + v = alc_mii_readreg_813x(sc, phy, reg); + return (v); +} +uint32_t +alc_mii_readreg_813x(struct alc_softc *sc, int phy, int reg) +{ uint32_t v; int i; - if (phy != sc->alc_phyaddr) return (0); @@ -180,15 +262,61 @@ alc_miibus_readreg(struct device *dev, i return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); } +uint32_t +alc_mii_readreg_816x(struct alc_softc *sc, int phy, int reg) +{ + uint32_t clk, v; + int i; + if ((sc->alc_flags & ALC_FLAG_LINK) != 0) + clk = MDIO_CLK_25_128; + else + clk = MDIO_CLK_25_4; + CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | + MDIO_SUP_PREAMBLE | clk | MDIO_REG_ADDR(reg)); + for (i = ALC_PHY_TIMEOUT; i > 0; i--) + { + DELAY(5); + v = CSR_READ_4(sc, ALC_MDIO); + if ((v & MDIO_OP_BUSY) == 0) + break; + } + if (i == 0) { + device_printf(sc , "phy read timeout : %d\n", reg); + return (0); + } + return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); +} + +int +alc_miibus_writeregr(struct device *dev, int phy, int reg, int val) +{ + int v; + struct alc_softc *sc = (struct alc_softc *)dev; + + if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) + v = alc_mii_writereg_816x(sc, phy, reg, val); + else + v = alc_mii_writereg_813x(sc, phy, reg, val); + return (v); +} + void alc_miibus_writereg(struct device *dev, int phy, int reg, int val) { + struct alc_softc *sc = (struct alc_softc *)dev; + if (phy != sc->alc_phyaddr) + return ; + + alc_miibus_writeregr(dev, phy, reg, val); +} + +uint32_t +alc_mii_writereg_813x(struct alc_softc *sc, int phy, int reg, int val) +{ uint32_t v; int i; - if (phy != sc->alc_phyaddr) - return; CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | @@ -201,8 +329,35 @@ alc_miibus_writereg(struct device *dev, } if (i == 0) + device_printf(sc, "phy write timeout : %d\n", reg); +return (0); +} + + +uint32_t +alc_mii_writereg_816x(struct alc_softc *sc, int phy, int reg, int val) +{ + uint32_t clk, v; + int i; + if ((sc->alc_flags & ALC_FLAG_LINK) != 0) + clk = MDIO_CLK_25_128; + else + clk = MDIO_CLK_25_4; + CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | + ((val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT) | MDIO_REG_ADDR(reg) | + MDIO_SUP_PREAMBLE | clk); + for (i = ALC_PHY_TIMEOUT; i > 0; i--) + { + DELAY(5); + v = CSR_READ_4(sc, ALC_MDIO); + if ((v & MDIO_OP_BUSY) == 0) + break; + } + if (i == 0) printf("%s: phy write timeout: phy %d, reg %d\n", sc->sc_dev.dv_xname, phy, reg); + + return (0); } void @@ -232,7 +387,6 @@ alc_miibus_statchg(struct device *dev) break; } } - alc_stop_queue(sc); /* Stop Rx/Tx MACs. */ alc_stop_mac(sc); @@ -244,10 +398,165 @@ alc_miibus_statchg(struct device *dev) reg = CSR_READ_4(sc, ALC_MAC_CFG); reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; CSR_WRITE_4(sc, ALC_MAC_CFG, reg); - alc_aspm(sc, IFM_SUBTYPE(mii->mii_media_active)); } + + alc_aspm(sc, 0, IFM_SUBTYPE(mii->mii_media_active)); + alc_dsp_fixup(sc, IFM_SUBTYPE(mii->mii_media_active)); +} + +uint32_t +alc_miidbg_readreg(struct alc_softc *sc, int reg) +{ + alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, reg); + return (alc_miibus_readreg(&sc->sc_dev, sc->alc_phyaddr, + ALC_MII_DBG_DATA)); +} + +uint32_t +alc_miidbg_writereg(struct alc_softc *sc, int reg, int val) +{ + alc_miibus_writereg(&sc->sc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, reg); + return alc_miibus_writeregr(&sc->sc_dev, sc->alc_phyaddr, + ALC_MII_DBG_DATA, val); +} + +uint32_t +alc_miiext_readreg(struct alc_softc *sc, int devaddr, int reg) +{ + uint32_t clk, v; + int i; + CSR_WRITE_4(sc, ALC_EXT_MDIO, EXT_MDIO_REG(reg) | + EXT_MDIO_DEVADDR(devaddr)); + if ((sc->alc_flags & ALC_FLAG_LINK) != 0) + clk = MDIO_CLK_25_128; + else + clk = MDIO_CLK_25_4; + CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | + MDIO_SUP_PREAMBLE | clk | MDIO_MODE_EXT); + for (i = ALC_PHY_TIMEOUT; i > 0; i--) + { + DELAY(5); + v = CSR_READ_4(sc, ALC_MDIO); + if ((v & MDIO_OP_BUSY) == 0) + break; + } + if (i == 0) + { + device_printf(sc, "phy ext read timeout : %d, %d\n", + devaddr, reg); + return (0); + } + return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); +} + +uint32_t +alc_miiext_writereg(struct alc_softc *sc, int devaddr, int reg, int val) +{ + uint32_t clk, v; + int i; + CSR_WRITE_4(sc, ALC_EXT_MDIO, EXT_MDIO_REG(reg) | + EXT_MDIO_DEVADDR(devaddr)); + if ((sc->alc_flags & ALC_FLAG_LINK) != 0) + clk = MDIO_CLK_25_128; + else + clk = MDIO_CLK_25_4; + CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | + ((val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT) | + MDIO_SUP_PREAMBLE | clk | MDIO_MODE_EXT); + for (i = ALC_PHY_TIMEOUT; i > 0; i--) + { + DELAY(5); + v = CSR_READ_4(sc, ALC_MDIO); + if ((v & MDIO_OP_BUSY) == 0) + break; + } + if (i == 0) + device_printf(sc, "phy ext write timeout : %d, %d\n", + devaddr, reg); + return (0); +} + +void +alc_dsp_fixup(struct alc_softc *sc, int media) +{ + uint16_t agc, len, val; + if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) + return; + if (AR816X_REV(sc->alc_rev) >= AR816X_REV_C0) + return; +/* +* Vendor PHY magic. +* 1000BT/AZ, wrong cable length +*/ + if ((sc->alc_flags & ALC_FLAG_LINK) != 0) + { + len = alc_miiext_readreg(sc, MII_EXT_PCS, MII_EXT_CLDCTL6); + len = (len >> EXT_CLDCTL6_CAB_LEN_SHIFT) & + EXT_CLDCTL6_CAB_LEN_MASK; + agc = alc_miidbg_readreg(sc, MII_DBG_AGC); + agc = (agc >> DBG_AGC_2_VGA_SHIFT) & DBG_AGC_2_VGA_MASK; + if ((media == IFM_1000_T && len > EXT_CLDCTL6_CAB_LEN_SHORT1G && + agc > DBG_AGC_LONG1G_LIMT) || + (media == IFM_100_TX && len > DBG_AGC_LONG100M_LIMT && + agc > DBG_AGC_LONG1G_LIMT)) + { + alc_miidbg_writereg(sc, MII_DBG_AZ_ANADECT, + DBG_AZ_ANADECT_LONG); + val = alc_miiext_readreg(sc, MII_EXT_ANEG, + MII_EXT_ANEG_AFE); + val |= ANEG_AFEE_10BT_100M_TH; + alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE, + val); + } + else + { + alc_miidbg_writereg(sc, MII_DBG_AZ_ANADECT, + DBG_AZ_ANADECT_DEFAULT); + val = alc_miiext_readreg(sc, MII_EXT_ANEG, + MII_EXT_ANEG_AFE); + val &= ~ANEG_AFEE_10BT_100M_TH; + alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE, + val); + } + if ((sc->alc_flags & ALC_FLAG_LINK_WAR) != 0 && + AR816X_REV(sc->alc_rev) == AR816X_REV_B0) + { + if (media == IFM_1000_T) + { +/* +* Giga link threshold, raise the tolerance of +* noise 50%. +*/ + val = alc_miidbg_readreg(sc, MII_DBG_MSE20DB); + val &= ~DBG_MSE20DB_TH_MASK; + val |= (DBG_MSE20DB_TH_HI << + DBG_MSE20DB_TH_SHIFT); + alc_miidbg_writereg(sc, MII_DBG_MSE20DB, val); + } + else if (media == IFM_100_TX) + alc_miidbg_writereg(sc, MII_DBG_MSE16DB, + DBG_MSE16DB_UP); + } + } + else + { + val = alc_miiext_readreg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE); + val &= ~ANEG_AFEE_10BT_100M_TH; + alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE, val); + if ((sc->alc_flags & ALC_FLAG_LINK_WAR) != 0 && + AR816X_REV(sc->alc_rev) == AR816X_REV_B0) { + alc_miidbg_writereg(sc, MII_DBG_MSE16DB, + DBG_MSE16DB_DOWN); + val = alc_miidbg_readreg(sc, MII_DBG_MSE20DB); + val &= ~DBG_MSE20DB_TH_MASK; + val |= (DBG_MSE20DB_TH_DEFAULT << DBG_MSE20DB_TH_SHIFT); + alc_miidbg_writereg(sc, MII_DBG_MSE20DB, val); + } + } } + + void alc_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) { @@ -290,7 +599,17 @@ alc_match(struct device *dev, void *matc void alc_get_macaddr(struct alc_softc *sc) { - uint32_t ea[2], opt; + if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) + alc_get_macaddr_816x(sc); + else + alc_get_macaddr_813x(sc); +} + +void +alc_get_macaddr_813x(struct alc_softc *sc) +{ + + uint32_t opt; uint16_t val; int eeprom, i; @@ -384,7 +703,76 @@ alc_get_macaddr(struct alc_softc *sc) break; } } + alc_get_macaddr_par(sc); +} + +void +alc_get_macaddr_816x(struct alc_softc *sc) +{ + uint32_t reg; + int i, reloaded; + reloaded = 0; +/* Try to reload station address via TWSI. */ + for (i = 100; i > 0; i--) + { + reg = CSR_READ_4(sc, ALC_SLD); + if ((reg & (SLD_PROGRESS | SLD_START)) == 0) + break; + DELAY(1000); + } + if (i != 0) + { + CSR_WRITE_4(sc, ALC_SLD, reg | SLD_START); + for (i = 100; i > 0; i--) + { + DELAY(1000); + reg = CSR_READ_4(sc, ALC_SLD); + if ((reg & SLD_START) == 0) + break; + } + if (i != 0) + reloaded++; + else if (alcdebug) + device_printf(sc, + "reloading station address via TWSI timed out!\n"); + } + /* Try to reload station address from EEPROM or FLASH. */ + if (reloaded == 0) + { + reg = CSR_READ_4(sc, ALC_EEPROM_LD); + if ((reg & (EEPROM_LD_EEPROM_EXIST | + EEPROM_LD_FLASH_EXIST)) != 0) { + for (i = 100; i > 0; i--) + { + reg = CSR_READ_4(sc, ALC_EEPROM_LD); + if ((reg & (EEPROM_LD_PROGRESS | + EEPROM_LD_START)) == 0) + break; + DELAY(1000); + } + if (i != 0) + { + CSR_WRITE_4(sc, ALC_EEPROM_LD, reg | + EEPROM_LD_START); + for (i = 100; i > 0; i--) + { + DELAY(1000); + reg = CSR_READ_4(sc, ALC_EEPROM_LD); + if ((reg & EEPROM_LD_START) == 0) + break; + } + } else if (alcdebug) + device_printf(sc, + "reloading EEPROM/FLASH timed out!\n"); + } + } + alc_get_macaddr_par(sc); +} +void +alc_get_macaddr_par(struct alc_softc *sc) +{ + uint32_t ea[2]; ea[0] = CSR_READ_4(sc, ALC_PAR0); ea[1] = CSR_READ_4(sc, ALC_PAR1); sc->alc_eaddr[0] = (ea[1] >> 8) & 0xFF; @@ -410,9 +798,20 @@ alc_disable_l0s_l1(struct alc_softc *sc) CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); } + + void alc_phy_reset(struct alc_softc *sc) { + if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) + alc_phy_reset_816x(sc); + else + alc_phy_reset_813x(sc); +} + +void +alc_phy_reset_813x(struct alc_softc *sc) +{ uint16_t data; /* Reset magic from Linux. */ @@ -524,10 +923,95 @@ alc_phy_reset(struct alc_softc *sc) data); } + + + +void +alc_phy_reset_816x(struct alc_softc *sc) +{ + uint32_t val; + val = CSR_READ_4(sc, ALC_GPHY_CFG); + val &= ~(GPHY_CFG_EXT_RESET | GPHY_CFG_LED_MODE | + GPHY_CFG_GATE_25M_ENB | GPHY_CFG_PHY_IDDQ | GPHY_CFG_PHY_PLL_ON | + GPHY_CFG_PWDOWN_HW | GPHY_CFG_100AB_ENB); + val |= GPHY_CFG_SEL_ANA_RESET; +#ifdef notyet + val |= GPHY_CFG_HIB_PULSE | GPHY_CFG_HIB_EN | GPHY_CFG_SEL_ANA_RESET; +#else + /* Disable PHY hibernation. */ + val &= ~(GPHY_CFG_HIB_PULSE | GPHY_CFG_HIB_EN); +#endif + CSR_WRITE_4(sc, ALC_GPHY_CFG, val); + DELAY(10); + CSR_WRITE_4(sc, ALC_GPHY_CFG, val | GPHY_CFG_EXT_RESET); + DELAY(800); +/* Vendor PHY magic. */ +#ifdef notyet + alc_miidbg_writereg(sc, MII_DBG_LEGCYPS, DBG_LEGCYPS_DEFAULT); + alc_miidbg_writereg(sc, MII_DBG_SYSMODCTL, DBG_SYSMODCTL_DEFAULT); + alc_miiext_writereg(sc, MII_EXT_PCS, MII_EXT_VDRVBIAS, + EXT_VDRVBIAS_DEFAULT); +#else + /* Disable PHY hibernation. */ + alc_miidbg_writereg(sc, MII_DBG_LEGCYPS, + DBG_LEGCYPS_DEFAULT & ~DBG_LEGCYPS_ENB); + alc_miidbg_writereg(sc, MII_DBG_HIBNEG, + DBG_HIBNEG_DEFAULT & ~(DBG_HIBNEG_PSHIB_EN | DBG_HIBNEG_HIB_PULSE)); + alc_miidbg_writereg(sc, MII_DBG_GREENCFG, DBG_GREENCFG_DEFAULT); +#endif + /* XXX Disable EEE. */ + val = CSR_READ_4(sc, ALC_LPI_CTL); + val &= ~LPI_CTL_ENB; + CSR_WRITE_4(sc, ALC_LPI_CTL, val); + alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_LOCAL_EEEADV, 0); + /* PHY power saving. */ + alc_miidbg_writereg(sc, MII_DBG_TST10BTCFG, DBG_TST10BTCFG_DEFAULT); + alc_miidbg_writereg(sc, MII_DBG_SRDSYSMOD, DBG_SRDSYSMOD_DEFAULT); + alc_miidbg_writereg(sc, MII_DBG_TST100BTCFG, DBG_TST100BTCFG_DEFAULT); + alc_miidbg_writereg(sc, MII_DBG_ANACTL, DBG_ANACTL_DEFAULT); + val = alc_miidbg_readreg(sc, MII_DBG_GREENCFG2); + val &= ~DBG_GREENCFG2_GATE_DFSE_EN; + alc_miidbg_writereg(sc, MII_DBG_GREENCFG2, val); + /* RTL8139C, 120m issue. */ + alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_NLP78, + ANEG_NLP78_120M_DEFAULT); + alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_S3DIG10, + ANEG_S3DIG10_DEFAULT); + if ((sc->alc_flags & ALC_FLAG_LINK_WAR) != 0) + { + /* Turn off half amplitude. */ + val = alc_miiext_readreg(sc, MII_EXT_PCS, MII_EXT_CLDCTL3); + val |= EXT_CLDCTL3_BP_CABLE1TH_DET_GT; + alc_miiext_writereg(sc, MII_EXT_PCS, MII_EXT_CLDCTL3, val); + /* Turn off Green feature. */ + val = alc_miidbg_readreg(sc, MII_DBG_GREENCFG2); + val |= DBG_GREENCFG2_BP_GREEN; + alc_miidbg_writereg(sc, MII_DBG_GREENCFG2, val); + /* Turn off half bias. */ + val = alc_miiext_readreg(sc, MII_EXT_PCS, MII_EXT_CLDCTL5); + val |= EXT_CLDCTL5_BP_VD_HLFBIAS; + alc_miiext_writereg(sc, MII_EXT_PCS, MII_EXT_CLDCTL5, val); + } +} + void alc_phy_down(struct alc_softc *sc) { + uint32_t gphy; switch (sc->sc_product) { + case PCI_PRODUCT_ATTANSIC_AR8161: + /*case DEVICEID_ATHEROS_E2200:*/ + case PCI_PRODUCT_ATTANSIC_AR8162: + case PCI_PRODUCT_ATTANSIC_AR8171: + case PCI_PRODUCT_ATTANSIC_AR8172: + gphy = CSR_READ_4(sc, ALC_GPHY_CFG); + gphy &= ~(GPHY_CFG_EXT_RESET | GPHY_CFG_LED_MODE | + GPHY_CFG_100AB_ENB | GPHY_CFG_PHY_PLL_ON); + gphy |= GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE | + GPHY_CFG_SEL_ANA_RESET; + gphy |= GPHY_CFG_PHY_IDDQ | GPHY_CFG_PWDOWN_HW; + CSR_WRITE_4(sc, ALC_GPHY_CFG, gphy); + break; case PCI_PRODUCT_ATTANSIC_L1D: case PCI_PRODUCT_ATTANSIC_L1D_1: /* @@ -555,7 +1039,15 @@ alc_phy_down(struct alc_softc *sc) } void -alc_aspm(struct alc_softc *sc, int media) +alc_aspm(struct alc_softc *sc, int init, int media) +{ + if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) + alc_aspm_816x(sc, init); + else + alc_aspm_813x(sc, media); +} +void +alc_aspm_813x(struct alc_softc *sc, int media) { uint32_t pmcfg; uint16_t linkcfg; @@ -638,6 +1130,174 @@ alc_aspm(struct alc_softc *sc, int media CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); } + +void +alc_aspm_816x(struct alc_softc *sc, int init) +{ + uint32_t pmcfg; + struct ifnet *ifp = &sc->sc_arpcom.ac_if; + pmcfg = CSR_READ_4(sc, ALC_PM_CFG); + pmcfg &= ~PM_CFG_L1_ENTRY_TIMER_816X_MASK; + pmcfg |= PM_CFG_L1_ENTRY_TIMER_816X_DEFAULT; + pmcfg &= ~PM_CFG_PM_REQ_TIMER_MASK; + pmcfg |= PM_CFG_PM_REQ_TIMER_816X_DEFAULT; + pmcfg &= ~PM_CFG_LCKDET_TIMER_MASK; + pmcfg |= PM_CFG_LCKDET_TIMER_DEFAULT; + pmcfg |= PM_CFG_SERDES_PD_EX_L1 | PM_CFG_CLK_SWH_L1 | PM_CFG_PCIE_RECV; + pmcfg &= ~(PM_CFG_RX_L1_AFTER_L0S | PM_CFG_TX_L1_AFTER_L0S | + PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB | + PM_CFG_SERDES_L1_ENB | PM_CFG_SERDES_PLL_L1_ENB | + PM_CFG_SERDES_BUDS_RX_L1_ENB | PM_CFG_SA_DLY_ENB | + PM_CFG_MAC_ASPM_CHK | PM_CFG_HOTRST); + if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 && + (sc->alc_rev & 0x01) != 0) + pmcfg |= PM_CFG_SERDES_L1_ENB | PM_CFG_SERDES_PLL_L1_ENB; + if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { + /* Link up, enable both L0s, L1s. */ + pmcfg |= PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB | + PM_CFG_MAC_ASPM_CHK; + } + else + { + if (init != 0) + pmcfg |= PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB | + PM_CFG_MAC_ASPM_CHK; + else if ((ifp->if_flags & IFF_RUNNING) != 0) + pmcfg |= PM_CFG_ASPM_L1_ENB | PM_CFG_MAC_ASPM_CHK; + } + CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); +} + +#define PCIEM_LINK_CAP_ASPM 0x00000c00 +#define PCIEM_LINK_CTL_RCB 0x0008 +#define PCIEM_LINK_CTL_ASPMC_DIS 0x0000 + #define PCIEM_LINK_CTL_ASPMC_L0S 0x0001 + #define PCIEM_LINK_CTL_ASPMC_L1 0x0002 + #define PCIEM_LINK_CTL_ASPMC 0x0003 + #define IFM_UNKNOWN 25 /* media types not defined yet */ + + + + void +alc_init_pcie(struct alc_softc *sc, int base) +{ + const char *aspm_state[] = { "L0s/L1", "L0s", "L1", "L0s/L1" }; + uint32_t cap, ctl, val; + int state; + + /* Clear data link and flow-control protocol error. */ + val = CSR_READ_4(sc, ALC_PEX_UNC_ERR_SEV); + val &= ~(PEX_UNC_ERR_SEV_DLP | PEX_UNC_ERR_SEV_FCP); + CSR_WRITE_4(sc, ALC_PEX_UNC_ERR_SEV, val); + if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) + { + CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG, + CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB); + CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, + CSR_READ_4(sc, ALC_PCIE_PHYMISC) | + PCIE_PHYMISC_FORCE_RCV_DET); + if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_1 && + sc->alc_rev == ATHEROS_AR8152_B_V10) + { + val = CSR_READ_4(sc, ALC_PCIE_PHYMISC2); + val &= ~(PCIE_PHYMISC2_SERDES_CDR_MASK | + PCIE_PHYMISC2_SERDES_TH_MASK); + val |= 3 << PCIE_PHYMISC2_SERDES_CDR_SHIFT; + val |= 3 << PCIE_PHYMISC2_SERDES_TH_SHIFT; + CSR_WRITE_4(sc, ALC_PCIE_PHYMISC2, val); + } + + /* Disable ASPM L0S and L1. */ + cap = pci_conf_read(sc->sc_pct, sc->sc_pcitag, + base + PCI_PCIE_LCAP) >> 16; + if ((cap & 0x00000c00) != 0) { + ctl = pci_conf_read(sc->sc_pct, sc->sc_pcitag, + base + PCI_PCIE_LCSR) >> 16; + if ((ctl & 0x08) != 0) + sc->alc_rcb = DMA_CFG_RCB_128; + if (alcdebug) + printf("%s: RCB %u bytes\n", + sc->sc_dev.dv_xname, + sc->alc_rcb == DMA_CFG_RCB_64 ? 64 : 128); + state = ctl & 0x03; + if (state & 0x01) + sc->alc_flags |= ALC_FLAG_L0S; + if (state & 0x02) + sc->alc_flags |= ALC_FLAG_L1S; + if (alcdebug) + printf("%s: ASPM %s %s\n", + sc->sc_dev.dv_xname, + aspm_state[state], + state == 0 ? "disabled" : "enabled"); + if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) + alc_disable_l0s_l1(sc); + } + else + { + if (alcdebug) + device_printf(sc, + "no ASPM support\n"); + } + } + else + { + val = CSR_READ_4(sc, ALC_PDLL_TRNS1); + val &= ~PDLL_TRNS1_D3PLLOFF_ENB; + CSR_WRITE_4(sc, ALC_PDLL_TRNS1, val); + val = CSR_READ_4(sc, ALC_MASTER_CFG); + if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 && + (sc->alc_rev & 0x01) != 0) + { + if ((val & MASTER_WAKEN_25M) == 0 || + (val & MASTER_CLK_SEL_DIS) == 0) { + val |= MASTER_WAKEN_25M | MASTER_CLK_SEL_DIS; + CSR_WRITE_4(sc, ALC_MASTER_CFG, val); + } + } + else + { + if ((val & MASTER_WAKEN_25M) == 0 || + (val & MASTER_CLK_SEL_DIS) != 0) { + val |= MASTER_WAKEN_25M; + val &= ~MASTER_CLK_SEL_DIS; + CSR_WRITE_4(sc, ALC_MASTER_CFG, val); + } + } + } + alc_aspm(sc, 1, IFM_UNKNOWN); +} + +void +alc_config_msi(struct alc_softc *sc) +{ + uint32_t ctl, mod; + if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) + { +/* +* It seems interrupt moderation is controlled by +* ALC_MSI_RETRANS_TIMER register if MSI/MSIX is active. +* Driver uses RX interrupt moderation parameter to +* program ALC_MSI_RETRANS_TIMER register. +*/ + ctl = CSR_READ_4(sc, ALC_MSI_RETRANS_TIMER); + ctl &= ~MSI_RETRANS_TIMER_MASK; + ctl &= ~MSI_RETRANS_MASK_SEL_LINE; + mod = ALC_USECS(sc->alc_int_rx_mod); + if (mod == 0) + mod = 1; + ctl |= mod; + if ((sc->alc_flags & ALC_FLAG_MSIX) != 0) + CSR_WRITE_4(sc, ALC_MSI_RETRANS_TIMER, ctl | + MSI_RETRANS_MASK_SEL_STD); + else if ((sc->alc_flags & ALC_FLAG_MSI) != 0) + CSR_WRITE_4(sc, ALC_MSI_RETRANS_TIMER, ctl | + MSI_RETRANS_MASK_SEL_LINE); + else + CSR_WRITE_4(sc, ALC_MSI_RETRANS_TIMER, 0); + } +} + + void alc_attach(struct device *parent, struct device *self, void *aux) { @@ -649,25 +1309,47 @@ alc_attach(struct device *parent, struct const char *intrstr; struct ifnet *ifp; pcireg_t memtype; - char *aspm_state[] = { "L0s/L1", "L0s", "L1", "L0s/L1" }; uint16_t burst; - int base, state, error = 0; - uint32_t cap, ctl, val; + int base, error = 0; /* * Allocate IO memory */ memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, ALC_PCIR_BAR); if (pci_mapreg_map(pa, ALC_PCIR_BAR, memtype, 0, &sc->sc_mem_bt, - &sc->sc_mem_bh, NULL, &sc->sc_mem_size, 0)) { + &sc->sc_mem_bh, NULL, &sc->sc_mem_size, 0)) + { printf(": can't map mem space\n"); return; } - if (pci_intr_map_msi(pa, &ih) != 0 && pci_intr_map(pa, &ih) != 0) { - printf(": can't map interrupt\n"); + if (pci_intr_map_msi(pa, &ih) != 0) + { + device_printf(sc, " can't map msi interrupt\n"); + if (pci_intr_map(pa, &ih) != 0) + { + device_printf(sc, " can't map interrupt\n"); goto fail; } + CSR_WRITE_4(sc, ALC_MSI_RETRANS_TIMER, 0); + + } + else /*msi*/ + { + int mod; + uint32_t msi_ctrl; + msi_ctrl = CSR_READ_4(sc, ALC_MSI_RETRANS_TIMER); + msi_ctrl &= ~MSI_RETRANS_TIMER_MASK; + msi_ctrl &= ~MSI_RETRANS_MASK_SEL_LINE; + mod = ALC_USECS(sc->alc_int_rx_mod); + if (mod == 0) + mod = 1; + msi_ctrl |= mod; + CSR_WRITE_4(sc, ALC_MSI_RETRANS_TIMER, msi_ctrl | + MSI_RETRANS_MASK_SEL_LINE); + + } + /* * Allocate IRQ @@ -675,14 +1357,15 @@ alc_attach(struct device *parent, struct intrstr = pci_intr_string(pc, ih); sc->sc_irq_handle = pci_intr_establish(pc, ih, IPL_NET, alc_intr, sc, sc->sc_dev.dv_xname); - if (sc->sc_irq_handle == NULL) { - printf(": could not establish interrupt"); + if (sc->sc_irq_handle == NULL) + { + device_printf(sc, " could not establish interrupt"); if (intrstr != NULL) - printf(" at %s", intrstr); + device_printf(sc, " at %s", intrstr); printf("\n"); goto fail; } - printf(": %s", intrstr); + device_printf(sc, " %s", intrstr); sc->sc_dmat = pa->pa_dmat; sc->sc_pct = pa->pa_pc; @@ -700,14 +1383,16 @@ alc_attach(struct device *parent, struct sc->alc_dma_wr_burst = 0; sc->alc_rcb = DMA_CFG_RCB_64; if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PCIEXPRESS, - &base, NULL)) { + &base, NULL)) + { sc->alc_flags |= ALC_FLAG_PCIE; sc->alc_expcap = base; burst = pci_conf_read(sc->sc_pct, sc->sc_pcitag, base + PCI_PCIE_DCSR) >> 16; sc->alc_dma_rd_burst = (burst & 0x7000) >> 12; sc->alc_dma_wr_burst = (burst & 0x00e0) >> 5; - if (alcdebug) { + if (alcdebug) + { printf("%s: Read request size : %u bytes.\n", sc->sc_dev.dv_xname, alc_dma_burst[sc->alc_dma_rd_burst]); @@ -720,53 +1405,13 @@ alc_attach(struct device *parent, struct if (alc_dma_burst[sc->alc_dma_wr_burst] > 1024) sc->alc_dma_wr_burst = 3; /* Clear data link and flow-control protocol error. */ - val = CSR_READ_4(sc, ALC_PEX_UNC_ERR_SEV); - val &= ~(PEX_UNC_ERR_SEV_DLP | PEX_UNC_ERR_SEV_FCP); - CSR_WRITE_4(sc, ALC_PEX_UNC_ERR_SEV, val); - CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG, - CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB); - CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, - CSR_READ_4(sc, ALC_PCIE_PHYMISC) | - PCIE_PHYMISC_FORCE_RCV_DET); - if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_1 && - sc->alc_rev == ATHEROS_AR8152_B_V10) { - val = CSR_READ_4(sc, ALC_PCIE_PHYMISC2); - val &= ~(PCIE_PHYMISC2_SERDES_CDR_MASK | - PCIE_PHYMISC2_SERDES_TH_MASK); - val |= 3 << PCIE_PHYMISC2_SERDES_CDR_SHIFT; - val |= 3 << PCIE_PHYMISC2_SERDES_TH_SHIFT; - CSR_WRITE_4(sc, ALC_PCIE_PHYMISC2, val); - } - /* Disable ASPM L0S and L1. */ - cap = pci_conf_read(sc->sc_pct, sc->sc_pcitag, - base + PCI_PCIE_LCAP) >> 16; - if ((cap & 0x00000c00) != 0) { - ctl = pci_conf_read(sc->sc_pct, sc->sc_pcitag, - base + PCI_PCIE_LCSR) >> 16; - if ((ctl & 0x08) != 0) - sc->alc_rcb = DMA_CFG_RCB_128; - if (alcdebug) - printf("%s: RCB %u bytes\n", - sc->sc_dev.dv_xname, - sc->alc_rcb == DMA_CFG_RCB_64 ? 64 : 128); - state = ctl & 0x03; - if (state & 0x01) - sc->alc_flags |= ALC_FLAG_L0S; - if (state & 0x02) - sc->alc_flags |= ALC_FLAG_L1S; - if (alcdebug) - printf("%s: ASPM %s %s\n", - sc->sc_dev.dv_xname, - aspm_state[state], - state == 0 ? "disabled" : "enabled"); - alc_disable_l0s_l1(sc); + alc_init_pcie(sc, base); } - } - /* Reset PHY. */ +/* Reset PHY. */ alc_phy_reset(sc); - - /* Reset the ethernet controller. */ +/* Reset the ethernet controller. */ + alc_stop_mac(sc); alc_reset(sc); /* @@ -776,7 +1421,20 @@ alc_attach(struct device *parent, struct * used in AR8132 can't establish gigabit link even if it * shows the same PHY model/revision number of AR8131. */ - switch (sc->sc_product) { + switch (sc->sc_product) + { + case PCI_PRODUCT_ATTANSIC_AR8161: + if (AR816X_REV(sc->alc_rev) ==0) + sc->alc_flags |= ALC_FLAG_LINK_WAR; + /* FALLTHROUGH */ + /*case DEVICEID_ATHEROS_E2200:*/ + case PCI_PRODUCT_ATTANSIC_AR8171: + sc->alc_flags |= ALC_FLAG_AR816X_FAMILY; + break; + case PCI_PRODUCT_ATTANSIC_AR8162: + case PCI_PRODUCT_ATTANSIC_AR8172: + sc->alc_flags |= ALC_FLAG_FASTETHER | ALC_FLAG_AR816X_FAMILY; + break; case PCI_PRODUCT_ATTANSIC_L2C_1: case PCI_PRODUCT_ATTANSIC_L2C_2: sc->alc_flags |= ALC_FLAG_APS; @@ -791,7 +1449,7 @@ alc_attach(struct device *parent, struct default: break; } - sc->alc_flags |= ALC_FLAG_ASPM_MON | ALC_FLAG_JUMBO; + sc->alc_flags |= ALC_FLAG_JUMBO; switch (sc->sc_product) { case PCI_PRODUCT_ATTANSIC_L1C: @@ -804,6 +1462,11 @@ alc_attach(struct device *parent, struct case PCI_PRODUCT_ATTANSIC_L2C_2: sc->alc_max_framelen = 6 * 1024; break; + default: + /* ALC_FLAG_AR816X_FAMILY*/ + sc->alc_max_framelen = 9 * 1024; + break; + } /* @@ -820,7 +1483,8 @@ alc_attach(struct device *parent, struct sc->alc_chip_rev = CSR_READ_4(sc, ALC_MASTER_CFG) >> MASTER_CHIP_REV_SHIFT; - if (alcdebug) { + if (alcdebug) + { printf("%s: PCI device revision : 0x%04x\n", sc->sc_dev.dv_xname, sc->alc_rev); printf("%s: Chip id/revision : 0x%04x\n", @@ -828,6 +1492,10 @@ alc_attach(struct device *parent, struct printf("%s: %u Tx FIFO, %u Rx FIFO\n", sc->sc_dev.dv_xname, CSR_READ_4(sc, ALC_SRAM_TX_FIFO_LEN) * 8, CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN) * 8); + if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) + device_printf(sc, "AR816x revision : 0x%x\n", + AR816X_REV(sc->alc_rev)); + } error = alc_dma_alloc(sc); @@ -859,7 +1527,7 @@ alc_attach(struct device *parent, struct ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING; #endif - printf(", address %s\n", ether_sprintf(sc->sc_arpcom.ac_enaddr)); + device_printf(sc, ", address %s\n", ether_sprintf(sc->sc_arpcom.ac_enaddr)); /* Set up MII bus. */ sc->sc_miibus.mii_ifp = ifp; @@ -892,6 +1560,7 @@ fail: pci_intr_disestablish(pc, sc->sc_irq_handle); if (sc->sc_mem_size) bus_space_unmap(sc->sc_mem_bt, sc->sc_mem_bh, sc->sc_mem_size); + } int @@ -1369,17 +2038,36 @@ alc_start(struct ifnet *ifp) struct alc_softc *sc = ifp->if_softc; struct mbuf *m_head; int enq = 0; + device_printf (sc," in alc_start ALC_INTR_MASK =0x%08x \n", + CSR_READ_4(sc, ALC_INTR_MASK)); + + + device_printf (sc, " in alc_start ALC_INTR_STATUS =0x%08x \n", + CSR_READ_4(sc, ALC_INTR_STATUS)); + /* Reclaim transmitted frames. */ if (sc->alc_cdata.alc_tx_cnt >= ALC_TX_DESC_HIWAT) alc_txeof(sc); if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) + { + device_printf (sc, " in alc_start ret A\n"); return; + } + + if ((sc->alc_flags & ALC_FLAG_LINK) == 0) + { + device_printf (sc, " in alc_start no link\n"); return; + } + if (IFQ_IS_EMPTY(&ifp->if_snd)) + { + device_printf (sc, ": in alc_start ret IFQ_IS_EMPTY \n"); return; + } for (;;) { IFQ_DEQUEUE(&ifp->if_snd, m_head); @@ -1392,8 +2080,14 @@ alc_start(struct ifnet *ifp) * for the NIC to drain the ring. */ if (alc_encap(sc, &m_head)) { + printf ("alc: in alc_start, alc_encap \n" ); + if (m_head == NULL) + { ifp->if_oerrors++; + printf ("alc: in alc_start, B m_head == NULL \n" ); + } + else { IF_PREPEND(&ifp->if_snd, m_head); ifp->if_flags |= IFF_OACTIVE; @@ -1401,6 +2095,7 @@ alc_start(struct ifnet *ifp) break; } enq++; + device_printf (sc, ": in alc_start enq = %d \n", enq ); #if NBPFILTER > 0 /* @@ -1418,11 +2113,17 @@ alc_start(struct ifnet *ifp) sc->alc_cdata.alc_tx_ring_map->dm_mapsize, BUS_DMASYNC_PREWRITE); /* Kick. Assume we're using normal Tx priority queue. */ + if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) + CSR_WRITE_2(sc, ALC_MBOX_TD_PRI0_PROD_IDX, + (uint16_t)sc->alc_cdata.alc_tx_prod); + else CSR_WRITE_4(sc, ALC_MBOX_TD_PROD_IDX, (sc->alc_cdata.alc_tx_prod << MBOX_TD_PROD_LO_IDX_SHIFT) & MBOX_TD_PROD_LO_IDX_MASK); /* Set a timeout in case the chip goes out to lunch. */ + device_printf (sc, ": Set a timeout in case the chip goes out to lunch. \n"); + ifp->if_timer = ALC_TX_TIMEOUT; } } @@ -1440,7 +2141,7 @@ alc_watchdog(struct ifnet *ifp) return; } - printf("%s: watchdog timeout\n", sc->sc_dev.dv_xname); + device_printf(sc, " watchdog timeout\n"); ifp->if_oerrors++; alc_init(ifp); alc_start(ifp); @@ -1510,7 +2211,8 @@ alc_mac_config(struct alc_softc *sc) reg = CSR_READ_4(sc, ALC_MAC_CFG); reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC | MAC_CFG_SPEED_MASK); - if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L1D || + if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0 || + sc->sc_product == PCI_PRODUCT_ATTANSIC_L1D || sc->sc_product == PCI_PRODUCT_ATTANSIC_L1D_1 || sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_2) reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW; @@ -1693,24 +2395,37 @@ alc_intr(void *arg) struct ifnet *ifp = &sc->sc_arpcom.ac_if; uint32_t status; int claimed = 0; + device_printf (sc,": in alc_intr \n"); status = CSR_READ_4(sc, ALC_INTR_STATUS); + device_printf (sc,": in alc_intr status = 0x%08x \n", status); + if ((status & ALC_INTRS) == 0) - return (0); + { + device_printf(sc,"a in alc_intr A return 0 \n"); + return (0); + } /* Disable interrupts. */ CSR_WRITE_4(sc, ALC_INTR_STATUS, INTR_DIS_INT); status = CSR_READ_4(sc, ALC_INTR_STATUS); if ((status & ALC_INTRS) == 0) - goto back; + { + device_printf (sc," in alc_intr A going \"back\" \n"); + goto back; + } /* Acknowledge and disable interrupts. */ CSR_WRITE_4(sc, ALC_INTR_STATUS, status | INTR_DIS_INT); if (ifp->if_flags & IFF_RUNNING) { if (status & INTR_RX_PKT) + { + device_printf (sc, ": in alc_intr calling alc_rxintr \n"); + alc_rxintr(sc); + } if (status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST | INTR_TXQ_TO_RST)) { @@ -1728,15 +2443,32 @@ alc_intr(void *arg) } if (status & INTR_TX_PKT) - alc_txeof(sc); + { + device_printf (sc, " alc_intr: calling alc_txeof(sc) \n"); + alc_txeof(sc); + } alc_start(ifp); } claimed = 1; back: /* Re-enable interrupts. */ + device_printf (sc, ": alc_intr: Re-enable interrupts \n"); + if ((ifp->if_flags & IFF_RUNNING) != 0) { + device_printf (sc, ", alc_intr: Re-enable interrupts \n"); + CSR_WRITE_4(sc, ALC_INTR_STATUS, 0x7FFFFFFF); + + device_printf (sc," in alc_start ALC_INTR_MASK =0x%08x \n", + CSR_READ_4(sc, ALC_INTR_MASK)); + + + device_printf (sc, " in alc_start ALC_INTR_STATUS =0x%08x \n", + CSR_READ_4(sc, ALC_INTR_STATUS)); + + + } return (claimed); } @@ -1747,9 +2479,13 @@ alc_txeof(struct alc_softc *sc) struct alc_txdesc *txd; uint32_t cons, prod; int prog; - + device_printf(sc," in alc_txeof \n"); if (sc->alc_cdata.alc_tx_cnt == 0) + { + device_printf(sc, " in alc_txeof ret A \n"); + return; + } bus_dmamap_sync(sc->sc_dmat, sc->alc_cdata.alc_tx_ring_map, 0, sc->alc_cdata.alc_tx_ring_map->dm_mapsize, BUS_DMASYNC_POSTWRITE); @@ -1758,11 +2494,19 @@ alc_txeof(struct alc_softc *sc) sc->alc_cdata.alc_cmb_map->dm_mapsize, BUS_DMASYNC_POSTREAD); prod = sc->alc_rdata.alc_cmb->cons; - } else + } + else + { + if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) + prod = CSR_READ_2(sc, ALC_MBOX_TD_PRI0_CONS_IDX); + else + { prod = CSR_READ_4(sc, ALC_MBOX_TD_CONS_IDX); /* Assume we're using normal Tx priority queue. */ prod = (prod & MBOX_TD_CONS_LO_IDX_MASK) >> MBOX_TD_CONS_LO_IDX_SHIFT; + } + } cons = sc->alc_cdata.alc_tx_cons; /* * Go through our Tx list and free mbufs for those @@ -1901,11 +2645,20 @@ alc_rxintr(struct alc_softc *sc) * it still seems that pre-fetching needs more * experimentation. */ + if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) + CSR_WRITE_2(sc, ALC_MBOX_RD0_PROD_IDX, + (uint16_t)sc->alc_cdata.alc_rx_cons); + else CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, sc->alc_cdata.alc_rx_cons); } } + + + + + /* Receive a frame. */ void alc_rxeof(struct alc_softc *sc, struct rx_rdesc *rrd) @@ -1920,6 +2673,7 @@ alc_rxeof(struct alc_softc *sc, struct r rdinfo = letoh32(rrd->rdinfo); rx_cons = RRD_RD_IDX(rdinfo); nsegs = RRD_RD_CNT(rdinfo); + device_printf(sc, " alc_rxeof \n"); sc->alc_cdata.alc_rxlen = RRD_BYTES(status); if (status & (RRD_ERR_SUM | RRD_ERR_LENGTH)) { @@ -1935,24 +2689,39 @@ alc_rxeof(struct alc_softc *sc, struct r * Force network stack compute checksum for * errored frames. */ + device_printf(sc, " alc: alc_rxeof B \n"); + if ((status & (RRD_ERR_CRC | RRD_ERR_ALIGN | RRD_ERR_TRUNC | RRD_ERR_RUNT)) != 0) + { + device_printf(sc, " alc_rxeof C \n"); + return; } + } for (count = 0; count < nsegs; count++, ALC_DESC_INC(rx_cons, ALC_RX_RING_CNT)) { + device_printf(sc, " alc: alc_rxeof D \n"); + rxd = &sc->alc_cdata.alc_rxdesc[rx_cons]; mp = rxd->rx_m; /* Add a new receive buffer to the ring. */ if (alc_newbuf(sc, rxd) != 0) { + device_printf(sc, " alc: alc_rxeof E \n"); + ifp->if_iqdrops++; /* Reuse Rx buffers. */ if (sc->alc_cdata.alc_rxhead != NULL) m_freem(sc->alc_cdata.alc_rxhead); + { + device_printf(sc, " alc: alc_rxeof F \n"); break; } + + } + /* * Assume we've received a full sized frame. * Actual size is fixed when we encounter the end of @@ -1962,10 +2731,12 @@ alc_rxeof(struct alc_softc *sc, struct r /* Chain received mbufs. */ if (sc->alc_cdata.alc_rxhead == NULL) { + device_printf(sc," alc_rxeof G\n"); sc->alc_cdata.alc_rxhead = mp; sc->alc_cdata.alc_rxtail = mp; } else { mp->m_flags &= ~M_PKTHDR; + device_printf(sc," alc_rxeof H\n"); sc->alc_cdata.alc_rxprev_tail = sc->alc_cdata.alc_rxtail; sc->alc_cdata.alc_rxtail->m_next = mp; @@ -1973,6 +2744,8 @@ alc_rxeof(struct alc_softc *sc, struct r } if (count == nsegs - 1) { + device_printf (sc, " alc_rxeof I\n"); + /* Last desc. for this frame. */ m = sc->alc_cdata.alc_rxhead; m->m_flags |= M_PKTHDR; @@ -1983,6 +2756,7 @@ alc_rxeof(struct alc_softc *sc, struct r m->m_pkthdr.len = sc->alc_cdata.alc_rxlen - ETHER_CRC_LEN; if (nsegs > 1) { + device_printf (sc, " alc_rxeof J\n"); /* Set last mbuf size. */ mp->m_len = sc->alc_cdata.alc_rxlen - (nsegs - 1) * sc->alc_buf_size; @@ -2020,11 +2794,15 @@ alc_rxeof(struct alc_softc *sc, struct r { /* Pass it on. */ + device_printf(sc," alc_rxeof: Pass it on \n"); + ether_input_mbuf(ifp, m); } } } /* Reset mbuf chains. */ + device_printf(sc," alc_rxeof: Reset mbuf chains \n"); + ALC_RXCHAIN_RESET(sc); } @@ -2044,14 +2822,76 @@ alc_tick(void *xsc) } void +alc_osc_reset(struct alc_softc *sc) +{ + uint32_t reg; + reg = CSR_READ_4(sc, ALC_MISC3); + reg &= ~MISC3_25M_BY_SW; + reg |= MISC3_25M_NOTO_INTNL; + CSR_WRITE_4(sc, ALC_MISC3, reg); + reg = CSR_READ_4(sc, ALC_MISC); + if (AR816X_REV(sc->alc_rev) >= AR816X_REV_B0) { +/* +* Restore over-current protection default value. +* This value could be reset by MAC reset. +*/ + reg &= ~MISC_PSW_OCP_MASK; + reg |= (MISC_PSW_OCP_DEFAULT << MISC_PSW_OCP_SHIFT); + reg &= ~MISC_INTNLOSC_OPEN; + CSR_WRITE_4(sc, ALC_MISC, reg); + CSR_WRITE_4(sc, ALC_MISC, reg | MISC_INTNLOSC_OPEN); + reg = CSR_READ_4(sc, ALC_MISC2); + reg &= ~MISC2_CALB_START; + CSR_WRITE_4(sc, ALC_MISC2, reg); + CSR_WRITE_4(sc, ALC_MISC2, reg | MISC2_CALB_START); + } + else + { + reg &= ~MISC_INTNLOSC_OPEN; +/* Disable isolate for revision A devices. */ + if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1) + reg &= ~MISC_ISO_ENB; + CSR_WRITE_4(sc, ALC_MISC, reg | MISC_INTNLOSC_OPEN); + CSR_WRITE_4(sc, ALC_MISC, reg); + } + DELAY(20); +} + +void alc_reset(struct alc_softc *sc) { uint32_t reg; int i; + uint32_t pmcfg = 0; - reg = CSR_READ_4(sc, ALC_MASTER_CFG) & 0xFFFF; + if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { + /* Reset workaround. */ + CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, 1); + if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 && + (sc->alc_rev & 0x01) != 0) { + /* Disable L0s/L1s before reset. */ + pmcfg = CSR_READ_4(sc, ALC_PM_CFG); + if ((pmcfg & (PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB)) + != 0) { + pmcfg &= ~(PM_CFG_ASPM_L0S_ENB | + PM_CFG_ASPM_L1_ENB); + CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); + } + } + } + reg = CSR_READ_4(sc, ALC_MASTER_CFG); reg |= MASTER_OOB_DIS_OFF | MASTER_RESET; CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); + + if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { + for (i = ALC_RESET_TIMEOUT; i > 0; i--) { + DELAY(10); + if (CSR_READ_4(sc, ALC_MBOX_RD0_PROD_IDX) == 0) + break; + } + if (i == 0) + printf( "MAC reset timeout!\n"); + } for (i = ALC_RESET_TIMEOUT; i > 0; i--) { DELAY(10); if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_RESET) == 0) @@ -2061,7 +2901,9 @@ alc_reset(struct alc_softc *sc) printf("%s: master reset timeout!\n", sc->sc_dev.dv_xname); for (i = ALC_RESET_TIMEOUT; i > 0; i--) { - if ((reg = CSR_READ_4(sc, ALC_IDLE_STATUS)) == 0) + reg = CSR_READ_4(sc, ALC_IDLE_STATUS); + if ((reg & (IDLE_STATUS_RXMAC | IDLE_STATUS_TXMAC | + IDLE_STATUS_RXQ | IDLE_STATUS_TXQ)) == 0) break; DELAY(10); } @@ -2069,8 +2911,40 @@ alc_reset(struct alc_softc *sc) if (i == 0) printf("%s: reset timeout(0x%08x)!\n", sc->sc_dev.dv_xname, reg); -} + if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { + if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 && + (sc->alc_rev & 0x01) != 0) { + reg = CSR_READ_4(sc, ALC_MASTER_CFG); + reg |= MASTER_CLK_SEL_DIS; + CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); +/* Restore L0s/L1s config. */ + if ((pmcfg & (PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB)) + != 0) + CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); + } + alc_osc_reset(sc); + reg = CSR_READ_4(sc, ALC_MISC3); + reg &= ~MISC3_25M_BY_SW; + reg |= MISC3_25M_NOTO_INTNL; + CSR_WRITE_4(sc, ALC_MISC3, reg); + reg = CSR_READ_4(sc, ALC_MISC); + reg &= ~MISC_INTNLOSC_OPEN; + if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1) + reg &= ~MISC_ISO_ENB; + CSR_WRITE_4(sc, ALC_MISC, reg); + DELAY(20); + } + if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0 || + sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_1 || + sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_2) + CSR_WRITE_4(sc, ALC_SERDES_LOCK, + CSR_READ_4(sc, ALC_SERDES_LOCK) | SERDES_MAC_CLK_SLOWDOWN | + SERDES_PHY_CLK_SLOWDOWN); +} +#if 0 +#define ALC_FLAG_ASPM_MON 0x0080 +#define ALC_RSS_IDT_TBL0 0x1B00 int alc_init(struct ifnet *ifp) { @@ -2117,6 +2991,7 @@ alc_init(struct ifnet *ifp) CSR_READ_4(sc, ALC_WOL_CFG); CSR_WRITE_4(sc, ALC_WOL_CFG, 0); /* Set Tx descriptor base addresses. */ + paddr = sc->alc_rdata.alc_tx_ring_paddr; CSR_WRITE_4(sc, ALC_TX_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); CSR_WRITE_4(sc, ALC_TDL_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); @@ -2295,13 +3170,14 @@ alc_init(struct ifnet *ifp) RX_FIFO_PAUSE_THRESH_HI_MASK)); } if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L1D_1 || + sc->sc_product == PCI_PRODUCT_ATTANSIC_AR8161 || sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_1) CSR_WRITE_4(sc, ALC_SERDES_LOCK, CSR_READ_4(sc, ALC_SERDES_LOCK) | SERDES_MAC_CLK_SLOWDOWN | SERDES_PHY_CLK_SLOWDOWN); /* Disable RSS until I understand L1C/L2C's RSS logic. */ - CSR_WRITE_4(sc, ALC_RSS_IDT_TABLE0, 0); + CSR_WRITE_4(sc, ALC_RSS_IDT_TBL0, 0); CSR_WRITE_4(sc, ALC_RSS_CPU, 0); /* Configure RxQ. */ @@ -2347,7 +3223,8 @@ alc_init(struct ifnet *ifp) reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX | ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & MAC_CFG_PREAMBLE_MASK); - if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L1D || + if (sc->sc_product == PCI_PRODUCT_ATTANSIC_AR8161|| + sc->sc_product == PCI_PRODUCT_ATTANSIC_L1D || sc->sc_product == PCI_PRODUCT_ATTANSIC_L1D_1 || sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_2) reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW; @@ -2363,16 +3240,21 @@ alc_init(struct ifnet *ifp) alc_rxvlan(sc); /* Acknowledge all pending interrupts and clear it. */ + CSR_WRITE_4(sc, ALC_INTR_MASK, ALC_INTRS ); + CSR_WRITE_4(sc, ALC_INTR_MASK, ALC_INTRS); - CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); - CSR_WRITE_4(sc, ALC_INTR_STATUS, 0); + CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); + CSR_WRITE_4(sc, ALC_INTR_STATUS , 0); + device_printf(sc, " alc_init alcflag link : A %d \n", sc-> alc_flags & ALC_FLAG_LINK); sc->alc_flags &= ~ALC_FLAG_LINK; + device_printf(sc, " alc_init alcflag link : AB %d \n", sc->alc_flags & ALC_FLAG_LINK); /* Switch to the current media. */ mii = &sc->sc_miibus; mii_mediachg(mii); + device_printf(sc, "alc_init : timeout_add_sec \n" ); - timeout_add_sec(&sc->alc_tick_ch, 1); + timeout_add_sec(&sc->alc_tick_ch, 3); ifp->if_flags |= IFF_RUNNING; ifp->if_flags &= ~IFF_OACTIVE; @@ -2380,6 +3262,415 @@ alc_init(struct ifnet *ifp) return (0); } +#else + +int +alc_init(struct ifnet *ifp) +{ + struct alc_softc *sc = ifp->if_softc; + uint8_t eaddr[ETHER_ADDR_LEN]; + bus_addr_t paddr; + uint32_t reg, rxf_hi, rxf_lo; + int error; + + /* + * Cancel any pending I/O. + */ + alc_stop(sc); + /* + * Reset the chip to a known state. + */ + alc_reset(sc); + + /* Initialize Rx descriptors. */ + error = alc_init_rx_ring(sc); + if (error != 0) { + printf("%s: no memory for Rx buffers.\n", sc->sc_dev.dv_xname); + alc_stop(sc); + return (error); + } + alc_init_rr_ring(sc); + alc_init_tx_ring(sc); + alc_init_cmb(sc); + alc_init_smb(sc); + + /* Enable all clocks. */ + if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { + CSR_WRITE_4(sc, ALC_CLK_GATING_CFG, CLK_GATING_DMAW_ENB | + CLK_GATING_DMAR_ENB | CLK_GATING_TXQ_ENB | + CLK_GATING_RXQ_ENB | CLK_GATING_TXMAC_ENB | + CLK_GATING_RXMAC_ENB); + if (AR816X_REV(sc->alc_rev) >= AR816X_REV_B0) + CSR_WRITE_4(sc, ALC_IDLE_DECISN_TIMER, + IDLE_DECISN_TIMER_DEFAULT_1MS); + } + else + CSR_WRITE_4(sc, ALC_CLK_GATING_CFG, 0); + + /* Reprogram the station address. */ + bcopy(LLADDR(ifp->if_sadl), eaddr, ETHER_ADDR_LEN); + CSR_WRITE_4(sc, ALC_PAR0, + eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); + CSR_WRITE_4(sc, ALC_PAR1, eaddr[0] << 8 | eaddr[1]); + /* + * Clear WOL status and disable all WOL feature as WOL + * would interfere Rx operation under normal environments. + */ + CSR_READ_4(sc, ALC_WOL_CFG); + CSR_WRITE_4(sc, ALC_WOL_CFG, 0); + /* Set Tx descriptor base addresses. */ + paddr = sc->alc_rdata.alc_tx_ring_paddr; + CSR_WRITE_4(sc, ALC_TX_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); + CSR_WRITE_4(sc, ALC_TDL_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); + /* We don't use high priority ring. */ + CSR_WRITE_4(sc, ALC_TDH_HEAD_ADDR_LO, 0); + /* Set Tx descriptor counter. */ + CSR_WRITE_4(sc, ALC_TD_RING_CNT, + (ALC_TX_RING_CNT << TD_RING_CNT_SHIFT) & TD_RING_CNT_MASK); + /* Set Rx descriptor base addresses. */ + paddr = sc->alc_rdata.alc_rx_ring_paddr; + CSR_WRITE_4(sc, ALC_RX_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); + CSR_WRITE_4(sc, ALC_RD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); + if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) + { + /* We use one Rx ring. */ + CSR_WRITE_4(sc, ALC_RD1_HEAD_ADDR_LO, 0); + CSR_WRITE_4(sc, ALC_RD2_HEAD_ADDR_LO, 0); + CSR_WRITE_4(sc, ALC_RD3_HEAD_ADDR_LO, 0); + } + /* Set Rx descriptor counter. */ + CSR_WRITE_4(sc, ALC_RD_RING_CNT, + (ALC_RX_RING_CNT << RD_RING_CNT_SHIFT) & RD_RING_CNT_MASK); + + /* + * Let hardware split jumbo frames into alc_max_buf_sized chunks. + * if it do not fit the buffer size. Rx return descriptor holds + * a counter that indicates how many fragments were made by the + * hardware. The buffer size should be multiple of 8 bytes. + * Since hardware has limit on the size of buffer size, always + * use the maximum value. + * For strict-alignment architectures make sure to reduce buffer + * size by 8 bytes to make room for alignment fixup. + */ + sc->alc_buf_size = RX_BUF_SIZE_MAX; + CSR_WRITE_4(sc, ALC_RX_BUF_SIZE, sc->alc_buf_size); + + paddr = sc->alc_rdata.alc_rr_ring_paddr; + /* Set Rx return descriptor base addresses. */ + CSR_WRITE_4(sc, ALC_RRD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); + if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) + { + /* We use one Rx return ring. */ + CSR_WRITE_4(sc, ALC_RRD1_HEAD_ADDR_LO, 0); + CSR_WRITE_4(sc, ALC_RRD2_HEAD_ADDR_LO, 0); + CSR_WRITE_4(sc, ALC_RRD3_HEAD_ADDR_LO, 0); + } + /* Set Rx return descriptor counter. */ + CSR_WRITE_4(sc, ALC_RRD_RING_CNT, + (ALC_RR_RING_CNT << RRD_RING_CNT_SHIFT) & RRD_RING_CNT_MASK); + paddr = sc->alc_rdata.alc_cmb_paddr; + CSR_WRITE_4(sc, ALC_CMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr)); + paddr = sc->alc_rdata.alc_smb_paddr; + CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); + CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr)); + + if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_1) { + /* Reconfigure SRAM - Vendor magic. */ + CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_LEN, 0x000002A0); + CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_LEN, 0x00000100); + CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_ADDR, 0x029F0000); + CSR_WRITE_4(sc, ALC_SRAM_RD0_ADDR, 0x02BF02A0); + CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_ADDR, 0x03BF02C0); + CSR_WRITE_4(sc, ALC_SRAM_TD_ADDR, 0x03DF03C0); + CSR_WRITE_4(sc, ALC_TXF_WATER_MARK, 0x00000000); + CSR_WRITE_4(sc, ALC_RD_DMA_CFG, 0x00000000); + } + + /* Tell hardware that we're ready to load DMA blocks. */ + CSR_WRITE_4(sc, ALC_DMA_BLOCK, DMA_BLOCK_LOAD); + + /* Configure interrupt moderation timer. */ + sc->alc_int_rx_mod = ALC_IM_RX_TIMER_DEFAULT; + sc->alc_int_tx_mod = ALC_IM_TX_TIMER_DEFAULT; + reg = ALC_USECS(sc->alc_int_rx_mod) << IM_TIMER_RX_SHIFT; + if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) + reg |= ALC_USECS(sc->alc_int_tx_mod) << IM_TIMER_TX_SHIFT; + CSR_WRITE_4(sc, ALC_IM_TIMER, reg); + /* + * We don't want to automatic interrupt clear as task queue + * for the interrupt should know interrupt status. + */ + reg = CSR_READ_4(sc, ALC_MASTER_CFG); + reg &= ~(MASTER_IM_RX_TIMER_ENB | MASTER_IM_TX_TIMER_ENB); + reg |= MASTER_SA_TIMER_ENB; + if (ALC_USECS(sc->alc_int_rx_mod) != 0) + reg |= MASTER_IM_RX_TIMER_ENB; + if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0 && + ALC_USECS(sc->alc_int_tx_mod) != 0) + reg |= MASTER_IM_TX_TIMER_ENB; + CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); + /* + * Disable interrupt re-trigger timer. We don't want automatic + * re-triggering of un-ACKed interrupts. + */ + CSR_WRITE_4(sc, ALC_INTR_RETRIG_TIMER, ALC_USECS(0)); + /* Configure CMB. */ + if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { + CSR_WRITE_4(sc, ALC_CMB_TD_THRESH, ALC_TX_RING_CNT / 3); + CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, + ALC_USECS(sc->alc_int_tx_mod)); + } + else + { + if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) + { + CSR_WRITE_4(sc, ALC_CMB_TD_THRESH, 4); + CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(5000)); + } + else + CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(0)); + } + /* + * Hardware can be configured to issue SMB interrupt based + * on programmed interval. Since there is a callout that is + * invoked for every hz in driver we use that instead of + * relying on periodic SMB interrupt. + */ + CSR_WRITE_4(sc, ALC_SMB_STAT_TIMER, ALC_USECS(0)); + /* Clear MAC statistics. */ + alc_stats_clear(sc); + + /* + * Always use maximum frame size that controller can support. + * Otherwise received frames that has larger frame length + * than alc(4) MTU would be silently dropped in hardware. This + * would make path-MTU discovery hard as sender wouldn't get + * any responses from receiver. alc(4) supports + * multi-fragmented frames on Rx path so it has no issue on + * assembling fragmented frames. Using maximum frame size also + * removes the need to reinitialize hardware when interface + * MTU configuration was changed. + * + * Be conservative in what you do, be liberal in what you + * accept from others - RFC 793. + */ + CSR_WRITE_4(sc, ALC_FRAME_SIZE, sc->alc_max_framelen); + + if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { + /* Disable header split(?) */ + CSR_WRITE_4(sc, ALC_HDS_CFG, 0); + + /* Configure IPG/IFG parameters. */ + CSR_WRITE_4(sc, ALC_IPG_IFG_CFG, + ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & + IPG_IFG_IPGT_MASK) | + ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & + IPG_IFG_MIFG_MASK) | + ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & + IPG_IFG_IPG1_MASK) | + ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & + IPG_IFG_IPG2_MASK)); +/* Set parameters for half-duplex media. */ + CSR_WRITE_4(sc, ALC_HDPX_CFG, + ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & + HDPX_CFG_LCOL_MASK) | + ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & + HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | + ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & + HDPX_CFG_ABEBT_MASK) | + ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & + HDPX_CFG_JAMIPG_MASK)); + } + /* + * Set TSO/checksum offload threshold. For frames that is + * larger than this threshold, hardware wouldn't do + * TSO/checksum offloading. + */ + reg = (sc->alc_max_framelen >> TSO_OFFLOAD_THRESH_UNIT_SHIFT) & + TSO_OFFLOAD_THRESH_MASK; + if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) + reg |= TSO_OFFLOAD_ERRLGPKT_DROP_ENB; + CSR_WRITE_4(sc, ALC_TSO_OFFLOAD_THRESH, reg); + /* Configure TxQ. */ + reg = (alc_dma_burst[sc->alc_dma_rd_burst] << + TXQ_CFG_TX_FIFO_BURST_SHIFT) & TXQ_CFG_TX_FIFO_BURST_MASK; + if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_1 || + sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_2) + reg >>= 1; + reg |= (TXQ_CFG_TD_BURST_DEFAULT << TXQ_CFG_TD_BURST_SHIFT) & + TXQ_CFG_TD_BURST_MASK; + reg |= TXQ_CFG_IP_OPTION_ENB | TXQ_CFG_8023_ENB; + CSR_WRITE_4(sc, ALC_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE); + if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) + { + reg = (TXQ_CFG_TD_BURST_DEFAULT << HQTD_CFG_Q1_BURST_SHIFT | + TXQ_CFG_TD_BURST_DEFAULT << HQTD_CFG_Q2_BURST_SHIFT | + TXQ_CFG_TD_BURST_DEFAULT << HQTD_CFG_Q3_BURST_SHIFT | + HQTD_CFG_BURST_ENB); + CSR_WRITE_4(sc, ALC_HQTD_CFG, reg); + reg = WRR_PRI_RESTRICT_NONE; + reg |= (WRR_PRI_DEFAULT << WRR_PRI0_SHIFT | + WRR_PRI_DEFAULT << WRR_PRI1_SHIFT | + WRR_PRI_DEFAULT << WRR_PRI2_SHIFT | + WRR_PRI_DEFAULT << WRR_PRI3_SHIFT); + CSR_WRITE_4(sc, ALC_WRR, reg); + } + else + { +/* Configure Rx free descriptor pre-fetching. */ + CSR_WRITE_4(sc, ALC_RX_RD_FREE_THRESH, + ((RX_RD_FREE_THRESH_HI_DEFAULT << + RX_RD_FREE_THRESH_HI_SHIFT) & RX_RD_FREE_THRESH_HI_MASK) | + ((RX_RD_FREE_THRESH_LO_DEFAULT << + RX_RD_FREE_THRESH_LO_SHIFT) & RX_RD_FREE_THRESH_LO_MASK)); + } + + + + + /* + * Configure flow control parameters. + * XON : 80% of Rx FIFO + * XOFF : 30% of Rx FIFO + */ + + if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) + { + reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN); + reg &= SRAM_RX_FIFO_LEN_MASK; + reg *= 8; + if (reg > 8 * 1024) + reg -= RX_FIFO_PAUSE_816X_RSVD; + else + reg -= RX_BUF_SIZE_MAX; + reg /= 8; + CSR_WRITE_4(sc, ALC_RX_FIFO_PAUSE_THRESH, + ((reg << RX_FIFO_PAUSE_THRESH_LO_SHIFT) & + RX_FIFO_PAUSE_THRESH_LO_MASK) | + (((RX_FIFO_PAUSE_816X_RSVD / 8) << + RX_FIFO_PAUSE_THRESH_HI_SHIFT) & + RX_FIFO_PAUSE_THRESH_HI_MASK)); + } + else if ( sc->sc_product == PCI_PRODUCT_ATTANSIC_L1C|| + sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C) { + reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN); + rxf_hi = (reg * 8) / 10; + rxf_lo = (reg * 3) / 10; + CSR_WRITE_4(sc, ALC_RX_FIFO_PAUSE_THRESH, + ((rxf_lo << RX_FIFO_PAUSE_THRESH_LO_SHIFT) & + RX_FIFO_PAUSE_THRESH_LO_MASK) | + ((rxf_hi << RX_FIFO_PAUSE_THRESH_HI_SHIFT) & + RX_FIFO_PAUSE_THRESH_HI_MASK)); + } + /* patch if (sc->sc_product == PCI_PRODUCT_ATTANSIC_L1D_1 || + sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_1) + CSR_WRITE_4(sc, ALC_SERDES_LOCK, + CSR_READ_4(sc, ALC_SERDES_LOCK) | SERDES_MAC_CLK_SLOWDOWN | + SERDES_PHY_CLK_SLOWDOWN); */ + if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) + { + /* Disable RSS until I understand L1C/L2C's RSS logic. */ + CSR_WRITE_4(sc, ALC_RSS_IDT_TABLE0, 0); + CSR_WRITE_4(sc, ALC_RSS_CPU, 0); + } + /* Configure RxQ. */ + reg = (RXQ_CFG_RD_BURST_DEFAULT << RXQ_CFG_RD_BURST_SHIFT) & + RXQ_CFG_RD_BURST_MASK; + reg |= RXQ_CFG_RSS_MODE_DIS; + if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) + reg |= (RXQ_CFG_816X_IDT_TBL_SIZE_DEFAULT << + RXQ_CFG_816X_IDT_TBL_SIZE_SHIFT) & + RXQ_CFG_816X_IDT_TBL_SIZE_MASK; + if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0 && + sc->sc_product != PCI_PRODUCT_ATTANSIC_L1D_1 ) + reg |= RXQ_CFG_ASPM_THROUGHPUT_LIMIT_1M; + CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); + + /* Configure DMA parameters. */ + reg = DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI; + reg |= sc->alc_rcb; + if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) + reg |= DMA_CFG_CMB_ENB; + if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) + reg |= DMA_CFG_SMB_ENB; + else + reg |= DMA_CFG_SMB_DIS; + reg |= (sc->alc_dma_rd_burst & DMA_CFG_RD_BURST_MASK) << + DMA_CFG_RD_BURST_SHIFT; + reg |= (sc->alc_dma_wr_burst & DMA_CFG_WR_BURST_MASK) << + DMA_CFG_WR_BURST_SHIFT; + reg |= (DMA_CFG_RD_DELAY_CNT_DEFAULT << DMA_CFG_RD_DELAY_CNT_SHIFT) & + DMA_CFG_RD_DELAY_CNT_MASK; + reg |= (DMA_CFG_WR_DELAY_CNT_DEFAULT << DMA_CFG_WR_DELAY_CNT_SHIFT) & + DMA_CFG_WR_DELAY_CNT_MASK; + + if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { + switch (AR816X_REV(sc->alc_rev)) { + case AR816X_REV_A0: + case AR816X_REV_A1: + reg |= DMA_CFG_RD_CHNL_SEL_1; + break; + case AR816X_REV_B0: + reg |= DMA_CFG_RD_CHNL_SEL_3; + break; + default: + break; + } + } + CSR_WRITE_4(sc, ALC_DMA_CFG, reg); + + /* + * Configure Tx/Rx MACs. + * - Auto-padding for short frames. + * - Enable CRC generation. + * Actual reconfiguration of MAC for resolved speed/duplex + * is followed after detection of link establishment. + * AR813x/AR815x always does checksum computation regardless + * of MAC_CFG_RXCSUM_ENB bit. Also the controller is known to + * have bug in protocol field in Rx return structure so + * these controllers can't handle fragmented frames. Disable + * Rx checksum offloading until there is a newer controller + * that has sane implementation. + */ + reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX | + ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & + MAC_CFG_PREAMBLE_MASK); + if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0 || + sc->sc_product == PCI_PRODUCT_ATTANSIC_L1D || + sc->sc_product == PCI_PRODUCT_ATTANSIC_L1D_1 || + sc->sc_product == PCI_PRODUCT_ATTANSIC_L2C_2) + reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW; + if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0) + reg |= MAC_CFG_SPEED_10_100; + else + reg |= MAC_CFG_SPEED_1000; + CSR_WRITE_4(sc, ALC_MAC_CFG, reg); + + /* Set up the receive filter. */ + alc_iff(sc); + + alc_rxvlan(sc); + + /* Acknowledge all pending interrupts and clear it. */ + CSR_WRITE_4(sc, ALC_INTR_MASK, ALC_INTRS); + CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); + CSR_WRITE_4(sc, ALC_INTR_STATUS, 0); + + ifp->if_flags |= IFF_RUNNING; + ifp->if_flags &= ~IFF_OACTIVE; + + + sc->alc_flags &= ~ALC_FLAG_LINK; + /* Switch to the current media. */ + alc_mediachange(ifp); + timeout_add_sec(&sc->alc_tick_ch, 1); + + ifp->if_flags |= IFF_RUNNING; + ifp->if_flags &= ~IFF_OACTIVE; + + return (0); +} +#endif void alc_stop(struct alc_softc *sc) { @@ -2403,7 +3694,6 @@ alc_stop(struct alc_softc *sc) /* Disable interrupts. */ CSR_WRITE_4(sc, ALC_INTR_MASK, 0); CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); - alc_stop_queue(sc); /* Disable DMA. */ reg = CSR_READ_4(sc, ALC_DMA_CFG); @@ -2418,6 +3708,9 @@ alc_stop(struct alc_softc *sc) /* Disable interrupts which might be touched in taskq handler. */ CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); + /* Disable L0s/L1s */ + alc_aspm(sc, 0, IFM_UNKNOWN); + /* Reclaim Rx buffers that have been processed. */ if (sc->alc_cdata.alc_rxhead != NULL) m_freem(sc->alc_cdata.alc_rxhead); @@ -2452,7 +3745,7 @@ alc_stop_mac(struct alc_softc *sc) { uint32_t reg; int i; - + alc_stop_queue(sc); /* Disable Rx/Tx MAC. */ reg = CSR_READ_4(sc, ALC_MAC_CFG); if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) { @@ -2461,7 +3754,7 @@ alc_stop_mac(struct alc_softc *sc) } for (i = ALC_TIMEOUT; i > 0; i--) { reg = CSR_READ_4(sc, ALC_IDLE_STATUS); - if (reg == 0) + if ((reg & (IDLE_STATUS_RXMAC | IDLE_STATUS_TXMAC)) == 0) break; DELAY(10); } @@ -2484,8 +3777,18 @@ alc_start_queue(struct alc_softc *sc) /* Enable RxQ. */ cfg = CSR_READ_4(sc, ALC_RXQ_CFG); + if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) + { + cfg &= ~RXQ_CFG_ENB; cfg |= qcfg[1]; + } + else + cfg |= RXQ_CFG_QUEUE0_ENB; + + + + CSR_WRITE_4(sc, ALC_RXQ_CFG, cfg); /* Enable TxQ. */ cfg = CSR_READ_4(sc, ALC_TXQ_CFG); @@ -2507,10 +3810,29 @@ alc_stop_queue(struct alc_softc *sc) } /* Disable TxQ. */ reg = CSR_READ_4(sc, ALC_TXQ_CFG); - if ((reg & TXQ_CFG_ENB) != 0) { - reg &= ~TXQ_CFG_ENB; - CSR_WRITE_4(sc, ALC_TXQ_CFG, reg); + if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { + if ((reg & RXQ_CFG_ENB) != 0) { + reg &= ~RXQ_CFG_ENB; + CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); + } + } else { + if ((reg & RXQ_CFG_QUEUE0_ENB) != 0) { + reg &= ~RXQ_CFG_QUEUE0_ENB; + CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); + } + } +#define ALC_EEPROM_LD 0x204 /* AR816x */ +#define EEPROM_LD_START 0x00000001 +#define EEPROM_LD_IDLE 0x00000010 +#define EEPROM_LD_DONE 0x00000000 +#define EEPROM_LD_PROGRESS 0x00000020 +#define EEPROM_LD_EXIST 0x00000100 +#define EEPROM_LD_EEPROM_EXIST 0x00000200 +#define EEPROM_LD_FLASH_EXIST 0x00000400 +#define EEPROM_LD_FLASH_END_ADDR_MASK 0x03FF0000 +#define EEPROM_LD_FLASH_END_ADDR_SHIFT 16 + DELAY(40); for (i = ALC_TIMEOUT; i > 0; i--) { reg = CSR_READ_4(sc, ALC_IDLE_STATUS); if ((reg & (IDLE_STATUS_RXQ | IDLE_STATUS_TXQ)) == 0) Index: if_alcreg.h =================================================================== RCS file: /home/vlado/cvsync/cvsroot/src/sys/dev/pci/if_alcreg.h,v retrieving revision 1.4 diff -u -p -r1.4 if_alcreg.h --- if_alcreg.h 25 May 2011 02:22:20 -0000 1.4 +++ if_alcreg.h 2 Nov 2014 13:59:54 -0000 @@ -1,5 +1,5 @@ /* $OpenBSD: if_alcreg.h,v 1.4 2011/05/25 02:22:20 kevlo Exp $ */ -/*- +/*- patched by oht to fit with the AR816X_FAMILY * Copyright (c) 2009, Pyun YongHyeon <[email protected]> * All rights reserved. * @@ -36,6 +36,18 @@ #define ATHEROS_AR8152_B_V10 0xC0 #define ATHEROS_AR8152_B_V11 0xC1 +/* + * Atheros AR816x/AR817x revisions + */ +#define AR816X_REV_A0 0 +#define AR816X_REV_A1 1 +#define AR816X_REV_B0 2 +#define AR816X_REV_C0 3 + +#define AR816X_REV_SHIFT 3 +#define AR816X_REV(x) ((x) >> AR816X_REV_SHIFT) + + /* 0x0000 - 0x02FF : PCIe configuration space */ #define ALC_PEX_UNC_ERR_SEV 0x10C @@ -51,11 +63,37 @@ #define PEX_UNC_ERR_SEV_ECRC 0x00080000 #define PEX_UNC_ERR_SEV_UR 0x00100000 +#define ALC_EEPROM_LD 0x204 /* AR816x */ +#define EEPROM_LD_START 0x00000001 +#define EEPROM_LD_IDLE 0x00000010 +#define EEPROM_LD_DONE 0x00000000 +#define EEPROM_LD_PROGRESS 0x00000020 +#define EEPROM_LD_EXIST 0x00000100 +#define EEPROM_LD_EEPROM_EXIST 0x00000200 +#define EEPROM_LD_FLASH_EXIST 0x00000400 +#define EEPROM_LD_FLASH_END_ADDR_MASK 0x03FF0000 +#define EEPROM_LD_FLASH_END_ADDR_SHIFT 16 + + #define ALC_TWSI_CFG 0x218 #define TWSI_CFG_SW_LD_START 0x00000800 #define TWSI_CFG_HW_LD_START 0x00001000 #define TWSI_CFG_LD_EXIST 0x00400000 + +#define ALC_SLD 0x218 /* AR816x */ +#define SLD_START 0x00000800 +#define SLD_PROGRESS 0x00001000 +#define SLD_IDLE 0x00002000 +#define SLD_SLVADDR_MASK 0x007F0000 +#define SLD_EXIST 0x00800000 +#define SLD_FREQ_MASK 0x03000000 +#define SLD_FREQ_100K 0x00000000 +#define SLD_FREQ_200K 0x01000000 +#define SLD_FREQ_300K 0x02000000 +#define SLD_FREQ_400K 0x03000000 + + #define ALC_PCIE_PHYMISC 0x1000 #define PCIE_PHYMISC_FORCE_RCV_DET 0x00000004 @@ -65,6 +103,9 @@ #define PCIE_PHYMISC2_SERDES_CDR_SHIFT 16 #define PCIE_PHYMISC2_SERDES_TH_SHIFT 18 +#define ALC_PDLL_TRNS1 0x1104 +#define PDLL_TRNS1_D3PLLOFF_ENB 0x00000800 + #define ALC_TWSI_DEBUG 0x1108 #define TWSI_DEBUG_DEV_EXIST 0x20000000 @@ -91,11 +132,15 @@ #define PM_CFG_SERDES_PD_EX_L1 0x00000040 #define PM_CFG_SERDES_BUDS_RX_L1_ENB 0x00000080 #define PM_CFG_L0S_ENTRY_TIMER_MASK 0x00000F00 +#define PM_CFG_RX_L1_AFTER_L0S 0x00000800 #define PM_CFG_ASPM_L0S_ENB 0x00001000 #define PM_CFG_CLK_SWH_L1 0x00002000 #define PM_CFG_CLK_PWM_VER1_1 0x00004000 #define PM_CFG_PCIE_RECV 0x00008000 #define PM_CFG_L1_ENTRY_TIMER_MASK 0x000F0000 +#define PM_CFG_L1_ENTRY_TIMER_816X_MASK 0x00070000 +#define PM_CFG_TX_L1_AFTER_L0S 0x00080000 + #define PM_CFG_PM_REQ_TIMER_MASK 0x00F00000 #define PM_CFG_LCKDET_TIMER_MASK 0x0F000000 #define PM_CFG_EN_BUFS_RX_L0S 0x10000000 @@ -109,8 +154,10 @@ #define PM_CFG_L0S_ENTRY_TIMER_DEFAULT 6 #define PM_CFG_L1_ENTRY_TIMER_DEFAULT 1 +#define PM_CFG_L1_ENTRY_TIMER_816X_DEFAULT 4 #define PM_CFG_LCKDET_TIMER_DEFAULT 12 #define PM_CFG_PM_REQ_TIMER_DEFAULT 12 +#define PM_CFG_PM_REQ_TIMER_816X_DEFAULT 15 #define ALC_LTSSM_ID_CFG 0x12FC #define LTSSM_ID_WRO_ENB 0x00001000 @@ -159,7 +206,9 @@ */ #define ALC_IM_TX_TIMER_DEFAULT 1000 /* 1ms */ -#define ALC_GPHY_CFG 0x140C /* 16bits */ + +#define ALC_GPHY_CFG 0x140C /* 16 bits, 32 bits on AR816x */ + #define GPHY_CFG_EXT_RESET 0x0001 #define GPHY_CFG_RTL_MODE 0x0002 #define GPHY_CFG_LED_MODE 0x0004 @@ -176,6 +225,7 @@ #define GPHY_CFG_PHY_PLL_ON 0x2000 #define GPHY_CFG_PWDOWN_HW 0x4000 #define GPHY_CFG_PHY_PLL_BYPASS 0x8000 +#define GPHY_CFG_100AB_ENB 0x00020000 #define ALC_IDLE_STATUS 0x1410 #define IDLE_STATUS_RXMAC 0x00000001 @@ -200,9 +250,10 @@ #define MDIO_CLK_25_10 0x04000000 #define MDIO_CLK_25_14 0x05000000 #define MDIO_CLK_25_20 0x06000000 -#define MDIO_CLK_25_28 0x07000000 +#define MDIO_CLK_25_128 0x07000000 #define MDIO_OP_BUSY 0x08000000 #define MDIO_AP_ENB 0x10000000 +#define MDIO_MODE_EXT 0x40000000 #define MDIO_DATA_SHIFT 0 #define MDIO_REG_ADDR_SHIFT 16 @@ -236,6 +287,23 @@ #define SERDES_MAC_CLK_SLOWDOWN 0x00020000 #define SERDES_PHY_CLK_SLOWDOWN 0x00040000 +#define ALC_LPI_CTL 0x1440 +#define LPI_CTL_ENB 0x00000001 + +#define ALC_EXT_MDIO 0x1448 +#define EXT_MDIO_REG_MASK 0x0000FFFF +#define EXT_MDIO_DEVADDR_MASK 0x001F0000 +#define EXT_MDIO_REG_SHIFT 0 +#define EXT_MDIO_DEVADDR_SHIFT 16 + +#define EXT_MDIO_REG(x) \ + (((x) << EXT_MDIO_REG_SHIFT) & EXT_MDIO_REG_MASK) +#define EXT_MDIO_DEVADDR(x) \ + (((x) << EXT_MDIO_DEVADDR_SHIFT) & EXT_MDIO_DEVADDR_MASK) + +#define ALC_IDLE_DECISN_TIMER 0x1474 +#define IDLE_DECISN_TIMER_DEFAULT_1MS 0x400 + #define ALC_MAC_CFG 0x1480 #define MAC_CFG_TX_ENB 0x00000001 #define MAC_CFG_RX_ENB 0x00000002 @@ -266,6 +334,7 @@ #define MAC_CFG_SINGLE_PAUSE_ENB 0x10000000 #define MAC_CFG_HASH_ALG_CRC32 0x20000000 #define MAC_CFG_SPEED_MODE_SW 0x40000000 +#define MAC_CFG_FAST_PAUSE 0x80000000 #define MAC_CFG_PREAMBLE_SHIFT 10 #define MAC_CFG_PREAMBLE_DEFAULT 7 @@ -366,8 +435,12 @@ #define ALC_RSS_IDT_TABLE0 0x14E0 +#define ALC_TD_PRI2_HEAD_ADDR_LO 0x14E0 /* AR816x */ + #define ALC_RSS_IDT_TABLE1 0x14E4 +#define ALC_TD_PRI3_HEAD_ADDR_LO 0x14E4 /* AR816x */ + #define ALC_RSS_IDT_TABLE2 0x14E8 #define ALC_RSS_IDT_TABLE3 0x14EC @@ -410,6 +483,9 @@ #define ALC_SRAM_RX_FIFO_ADDR 0x1520 #define ALC_SRAM_RX_FIFO_LEN 0x1524 +#define SRAM_RX_FIFO_LEN_MASK 0x00000FFF +#define SRAM_RX_FIFO_LEN_SHIFT 0 + #define ALC_SRAM_TX_FIFO_ADDR 0x1528 @@ -466,8 +542,12 @@ #define ALC_TDH_HEAD_ADDR_LO 0x157C +#define ALC_TD_PRI1_HEAD_ADDR_LO 0x157C /* AR816x */ + #define ALC_TDL_HEAD_ADDR_LO 0x1580 +#define ALC_TD_PRI0_HEAD_ADDR_LO 0x1580 /* AR816x */ + #define ALC_TD_RING_CNT 0x1584 #define TD_RING_CNT_MASK 0x0000FFFF #define TD_RING_CNT_SHIFT 0 @@ -487,6 +567,7 @@ #define ALC_TSO_OFFLOAD_THRESH 0x1594 /* 8 bytes unit */ #define TSO_OFFLOAD_THRESH_MASK 0x000007FF +#define TSO_OFFLOAD_ERRLGPKT_DROP_ENB 0x00000800 #define TSO_OFFLOAD_THRESH_SHIFT 0 #define TSO_OFFLOAD_THRESH_UNIT 8 #define TSO_OFFLOAD_THRESH_UNIT_SHIFT 3 @@ -534,6 +615,17 @@ (RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB | \ RXQ_CFG_QUEUE2_ENB | RXQ_CFG_QUEUE3_ENB) +/* AR816x specific bits */ +#define RXQ_CFG_816X_RSS_HASH_IPV4 0x00000004 +#define RXQ_CFG_816X_RSS_HASH_IPV4_TCP 0x00000008 +#define RXQ_CFG_816X_RSS_HASH_IPV6 0x00000010 +#define RXQ_CFG_816X_RSS_HASH_IPV6_TCP 0x00000020 +#define RXQ_CFG_816X_RSS_HASH_MASK 0x0000003C +#define RXQ_CFG_816X_IPV6_PARSE_ENB 0x00000080 +#define RXQ_CFG_816X_IDT_TBL_SIZE_MASK 0x0001FF00 +#define RXQ_CFG_816X_IDT_TBL_SIZE_SHIFT 8 +#define RXQ_CFG_816X_IDT_TBL_SIZE_DEFAULT 0x100 + #define ALC_RX_RD_FREE_THRESH 0x15A4 /* 8 bytes unit. */ #define RX_RD_FREE_THRESH_HI_MASK 0x0000003F #define RX_RD_FREE_THRESH_LO_MASK 0x00000FC0 @@ -548,6 +640,13 @@ #define RX_FIFO_PAUSE_THRESH_LO_SHIFT 0 #define RX_FIFO_PAUSE_THRESH_HI_SHIFT 16 +/* + * Size = tx-packet(1522) IPG(12) + SOF(8) + 64(Pause) + IPG(12) + SOF(8) + + * rx-packet(1522) + delay-of-link(64) + * = 3212. + */ +#define RX_FIFO_PAUSE_816X_RSVD 3212 + #define ALC_RD_DMA_CFG 0x15AC #define RD_DMA_CFG_THRESH_MASK 0x00000FFF /* 8 bytes unit */ #define RD_DMA_CFG_TIMER_MASK 0xFFFF0000 @@ -589,6 +688,14 @@ #define DMA_CFG_SMB_ENB 0x00200000 #define DMA_CFG_CMB_NOW 0x00400000 #define DMA_CFG_SMB_DIS 0x01000000 +#define DMA_CFG_RD_CHNL_SEL_MASK 0x0C000000 +#define DMA_CFG_RD_CHNL_SEL_1 0x00000000 +#define DMA_CFG_RD_CHNL_SEL_2 0x04000000 +#define DMA_CFG_RD_CHNL_SEL_3 0x08000000 +#define DMA_CFG_RD_CHNL_SEL_4 0x0C000000 +#define DMA_CFG_WSRAM_RDCTL 0x10000000 +#define DMA_CFG_RD_PEND_CLR 0x20000000 +#define DMA_CFG_WR_PEND_CLR 0x40000000 #define DMA_CFG_SMB_NOW 0x80000000 #define DMA_CFG_RD_BURST_MASK 0x07 #define DMA_CFG_RD_BURST_SHIFT 4 @@ -611,6 +718,12 @@ #define CMB_TX_TIMER_MASK 0x0000FFFF #define CMB_TX_TIMER_SHIFT 0 +#define ALC_MSI_MAP_TBL1 0x15D0 + +#define ALC_MSI_ID_MAP 0x15D4 + +#define ALC_MSI_MAP_TBL2 0x15D8 + #define ALC_MBOX_RD0_PROD_IDX 0x15E0 #define ALC_MBOX_RD1_PROD_IDX 0x15E4 @@ -628,12 +741,21 @@ #define MBOX_TD_PROD_HI_IDX_SHIFT 0 #define MBOX_TD_PROD_LO_IDX_SHIFT 16 +#define ALC_MBOX_TD_PRI1_PROD_IDX 0x15F0 /* 16 bits AR816x */ + +#define ALC_MBOX_TD_PRI0_PROD_IDX 0x15F2 /* 16 bits AR816x */ + + #define ALC_MBOX_TD_CONS_IDX 0x15F4 #define MBOX_TD_CONS_HI_IDX_MASK 0x0000FFFF #define MBOX_TD_CONS_LO_IDX_MASK 0xFFFF0000 #define MBOX_TD_CONS_HI_IDX_SHIFT 0 #define MBOX_TD_CONS_LO_IDX_SHIFT 16 +#define ALC_MBOX_TD_PRI1_CONS_IDX 0x15F4 /* 16 bits AR816x */ + +#define ALC_MBOX_TD_PRI0_CONS_IDX 0x15F6 /* 16 bits AR816x */ + #define ALC_MBOX_RD01_CONS_IDX 0x15F8 #define MBOX_RD0_CONS_IDX_MASK 0x0000FFFF #define MBOX_RD1_CONS_IDX_MASK 0xFFFF0000 @@ -662,7 +784,7 @@ #define INTR_GPHY 0x00001000 #define INTR_GPHY_LOW_PW 0x00002000 #define INTR_TXQ_TO_RST 0x00004000 -#define INTR_TX_PKT 0x00008000 +#define INTR_TX_PKT0 0x00008000 #define INTR_RX_PKT0 0x00010000 #define INTR_RX_PKT1 0x00020000 #define INTR_RX_PKT2 0x00040000 @@ -676,6 +798,16 @@ #define INTR_PHY_LINK_DOWN 0x04000000 #define INTR_DIS_INT 0x80000000 +/* INTR status for AR816x/AR817x 4 TX queues, 8 RX queues */ +#define INTR_TX_PKT1 0x00000020 +#define INTR_TX_PKT2 0x00000040 +#define INTR_TX_PKT3 0x00000080 +#define INTR_RX_PKT4 0x08000000 +#define INTR_RX_PKT5 0x10000000 +#define INTR_RX_PKT6 0x20000000 +#define INTR_RX_PKT7 0x40000000 + + /* Interrupt Mask Register */ #define ALC_INTR_MASK 0x1604 @@ -687,16 +819,19 @@ (INTR_RD0_UNDERRUN | INTR_RD1_UNDERRUN | \ INTR_RD2_UNDERRUN | INTR_RD3_UNDERRUN) #else +#define INTR_TX_PKT INTR_TX_PKT0 #define INTR_RX_PKT INTR_RX_PKT0 #define INTR_RD_UNDERRUN INTR_RD0_UNDERRUN #endif - +#if 0 #define ALC_INTRS \ (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST | \ INTR_TXQ_TO_RST | INTR_RX_PKT | INTR_TX_PKT | \ INTR_RX_FIFO_OFLOW | INTR_RD_UNDERRUN | \ INTR_TX_FIFO_UNDERRUN) - +#else +#define ALC_INTRS 0x00018000 +#endif #define ALC_INTR_RETRIG_TIMER 0x1608 #define INTR_RETRIG_TIMER_MASK 0x0000FFFF #define INTR_RETRIG_TIMER_SHIFT 0 @@ -708,11 +843,56 @@ #define HDS_CFG_BACKFILLSIZE_SHIFT 8 #define HDS_CFG_MAX_HDRSIZE_SHIFT 20 +#define ALC_MBOX_TD_PRI3_PROD_IDX 0x1618 /* 16 bits AR816x */ + +#define ALC_MBOX_TD_PRI2_PROD_IDX 0x161A /* 16 bits AR816x */ + +#define ALC_MBOX_TD_PRI3_CONS_IDX 0x161C /* 16 bits AR816x */ + +#define ALC_MBOX_TD_PRI2_CONS_IDX 0x161E /* 16 bits AR816x */ + + /* AR813x/AR815x registers for MAC statistics */ #define ALC_RX_MIB_BASE 0x1700 #define ALC_TX_MIB_BASE 0x1760 +#define ALC_DRV 0x1804 /* AR816x */ +#define DRV_ASPM_SPD10LMT_1M 0x00000000 +#define DRV_ASPM_SPD10LMT_10M 0x00000001 +#define DRV_ASPM_SPD10LMT_100M 0x00000002 +#define DRV_ASPM_SPD10LMT_NO 0x00000003 +#define DRV_ASPM_SPD10LMT_MASK 0x00000003 +#define DRV_ASPM_SPD100LMT_1M 0x00000000 +#define DRV_ASPM_SPD100LMT_10M 0x00000004 +#define DRV_ASPM_SPD100LMT_100M 0x00000008 +#define DRV_ASPM_SPD100LMT_NO 0x0000000C +#define DRV_ASPM_SPD100LMT_MASK 0x0000000C +#define DRV_ASPM_SPD1000LMT_100M 0x00000000 +#define DRV_ASPM_SPD1000LMT_NO 0x00000010 +#define DRV_ASPM_SPD1000LMT_1M 0x00000020 +#define DRV_ASPM_SPD1000LMT_10M 0x00000030 +#define DRV_ASPM_SPD1000LMT_MASK 0x00000000 +#define DRV_WOLCAP_BIOS_EN 0x00000100 +#define DRV_WOLMAGIC_EN 0x00000200 +#define DRV_WOLLINKUP_EN 0x00000400 +#define DRV_WOLPATTERN_EN 0x00000800 +#define DRV_AZ_EN 0x00001000 +#define DRV_WOLS5_BIOS_EN 0x00010000 +#define DRV_WOLS5_EN 0x00020000 +#define DRV_DISABLE 0x00040000 +#define DRV_PHY_MASK 0x1FE00000 +#define DRV_PHY_EEE 0x00200000 +#define DRV_PHY_APAUSE 0x00400000 +#define DRV_PHY_PAUSE 0x00800000 +#define DRV_PHY_DUPLEX 0x01000000 +#define DRV_PHY_10 0x02000000 +#define DRV_PHY_100 0x04000000 +#define DRV_PHY_1000 0x08000000 +#define DRV_PHY_AUTO 0x10000000 +#define DRV_PHY_SHIFT 21 + + #define ALC_CLK_GATING_CFG 0x1814 #define CLK_GATING_DMAW_ENB 0x0001 #define CLK_GATING_DMAR_ENB 0x0002 @@ -725,6 +905,53 @@ #define ALC_DEBUG_DATA1 0x1904 +#define ALC_MSI_RETRANS_TIMER 0x1920 +#define MSI_RETRANS_TIMER_MASK 0x0000FFFF +#define MSI_RETRANS_MASK_SEL_STD 0x00000000 +#define MSI_RETRANS_MASK_SEL_LINE 0x00010000 +#define MSI_RETRANS_TIMER_SHIFT 0 + +#define ALC_WRR 0x1938 +#define WRR_PRI0_MASK 0x0000001F +#define WRR_PRI1_MASK 0x00001F00 +#define WRR_PRI2_MASK 0x001F0000 +#define WRR_PRI3_MASK 0x1F000000 +#define WRR_PRI_RESTRICT_MASK 0x60000000 +#define WRR_PRI_RESTRICT_ALL 0x00000000 +#define WRR_PRI_RESTRICT_HI 0x20000000 +#define WRR_PRI_RESTRICT_HI2 0x40000000 +#define WRR_PRI_RESTRICT_NONE 0x60000000 +#define WRR_PRI0_SHIFT 0 +#define WRR_PRI1_SHIFT 8 +#define WRR_PRI2_SHIFT 16 +#define WRR_PRI3_SHIFT 24 +#define WRR_PRI_DEFAULT 4 +#define WRR_PRI_RESTRICT_SHIFT 29 + +#define ALC_HQTD_CFG 0x193C +#define HQTD_CFG_Q1_BURST_MASK 0x0000000F +#define HQTD_CFG_Q2_BURST_MASK 0x000000F0 +#define HQTD_CFG_Q3_BURST_MASK 0x00000F00 +#define HQTD_CFG_BURST_ENB 0x80000000 +#define HQTD_CFG_Q1_BURST_SHIFT 0 +#define HQTD_CFG_Q2_BURST_SHIFT 4 +#define HQTD_CFG_Q3_BURST_SHIFT 8 + +#define ALC_MISC 0x19C0 +#define MISC_INTNLOSC_OPEN 0x00000008 +#define MISC_ISO_ENB 0x00001000 +#define MISC_PSW_OCP_MASK 0x00E00000 +#define MISC_PSW_OCP_SHIFT 21 +#define MISC_PSW_OCP_DEFAULT 7 + +#define ALC_MISC2 0x19C8 +#define MISC2_CALB_START 0x00000001 + +#define ALC_MISC3 0x19CC +#define MISC3_25M_NOTO_INTNL 0x00000001 +#define MISC3_25M_BY_SW 0x00000002 + + #define ALC_MII_DBG_ADDR 0x1D #define ALC_MII_DBG_DATA 0x1E @@ -744,6 +971,10 @@ #define ANA_SEL_CLK125M_DSP 0x8000 #define ANA_MANUL_SWICH_ON_SHIFT 1 +#define MII_DBG_ANACTL 0x00 +#define DBG_ANACTL_DEFAULT 0x02EF + + #define MII_ANA_CFG4 0x04 #define ANA_IECHO_ADJ_MASK 0x0F #define ANA_IECHO_ADJ_3_MASK 0x000F @@ -755,6 +986,9 @@ #define ANA_IECHO_ADJ_1_SHIFT 8 #define ANA_IECHO_ADJ_0_SHIFT 12 +#define MII_DBG_SYSMODCTL 0x04 +#define DBG_SYSMODCTL_DEFAULT 0xBB8B + #define MII_ANA_CFG5 0x05 #define ANA_SERDES_CDR_BW_MASK 0x0003 #define ANA_MS_PAD_DBG 0x0004 @@ -771,9 +1005,17 @@ #define ANA_SERDES_CDR_BW_SHIFT 0 #define ANA_SERDES_TH_LOS_SHIFT 4 +#define MII_DBG_SRDSYSMOD 0x05 +#define DBG_SRDSYSMOD_DEFAULT 0x2C46 + #define MII_ANA_CFG11 0x0B #define ANA_PS_HIB_EN 0x8000 +#define MII_DBG_HIBNEG 0x0B +#define DBG_HIBNEG_HIB_PULSE 0x1000 +#define DBG_HIBNEG_PSHIB_EN 0x8000 +#define DBG_HIBNEG_DEFAULT 0xBC40 + #define MII_ANA_CFG18 0x12 #define ANA_TEST_MODE_10BT_01MASK 0x0003 #define ANA_LOOP_SEL_10BT 0x0004 @@ -788,9 +1030,37 @@ #define ANA_TRIGGER_SEL_TIMER_SHIFT 12 #define ANA_INTERVAL_SEL_TIMER_SHIFT 14 +#define MII_DBG_TST10BTCFG 0x12 +#define DBG_TST10BTCFG_DEFAULT 0x4C04 + +#define MII_DBG_AZ_ANADECT 0x15 +#define DBG_AZ_ANADECT_DEFAULT 0x3220 +#define DBG_AZ_ANADECT_LONG 0x3210 + +#define MII_DBG_MSE16DB 0x18 +#define DBG_MSE16DB_UP 0x05EA +#define DBG_MSE16DB_DOWN 0x02EA + +#define MII_DBG_MSE20DB 0x1C +#define DBG_MSE20DB_TH_MASK 0x01FC +#define DBG_MSE20DB_TH_DEFAULT 0x2E +#define DBG_MSE20DB_TH_HI 0x54 +#define DBG_MSE20DB_TH_SHIFT 2 + +#define MII_DBG_AGC 0x23 +#define DBG_AGC_2_VGA_MASK 0x3F00 +#define DBG_AGC_2_VGA_SHIFT 8 +#define DBG_AGC_LONG1G_LIMT 40 +#define DBG_AGC_LONG100M_LIMT 44 + #define MII_ANA_CFG41 0x29 #define ANA_TOP_PS_EN 0x8000 +#define MII_DBG_LEGCYPS 0x29 +#define DBG_LEGCYPS_ENB 0x8000 +#define DBG_LEGCYPS_DEFAULT 0x129D + + #define MII_ANA_CFG54 0x36 #define ANA_LONG_CABLE_TH_100_MASK 0x003F #define ANA_DESERVED 0x0040 @@ -801,6 +1071,52 @@ #define ANA_LONG_CABLE_TH_100_SHIFT 0 #define ANA_SHORT_CABLE_TH_100_SHIFT 8 + +#define MII_DBG_TST100BTCFG 0x36 +#define DBG_TST100BTCFG_DEFAULT 0xE12C + +#define MII_DBG_GREENCFG 0x3B +#define DBG_GREENCFG_DEFAULT 0x7078 + +#define MII_DBG_GREENCFG2 0x3D +#define DBG_GREENCFG2_GATE_DFSE_EN 0x0080 +#define DBG_GREENCFG2_BP_GREEN 0x8000 + +/* Device addr 3 */ +#define MII_EXT_PCS 3 + +#define MII_EXT_CLDCTL3 0x8003 +#define EXT_CLDCTL3_BP_CABLE1TH_DET_GT 0x8000 + +#define MII_EXT_CLDCTL5 0x8005 +#define EXT_CLDCTL5_BP_VD_HLFBIAS 0x4000 + +#define MII_EXT_CLDCTL6 0x8006 +#define EXT_CLDCTL6_CAB_LEN_MASK 0x00FF +#define EXT_CLDCTL6_CAB_LEN_SHIFT 0 +#define EXT_CLDCTL6_CAB_LEN_SHORT1G 116 +#define EXT_CLDCTL6_CAB_LEN_SHORT100M 152 + +#define MII_EXT_VDRVBIAS 0x8062 +#define EXT_VDRVBIAS_DEFAULT 3 + +/* Device addr 7 */ +#define MII_EXT_ANEG 7 + +#define MII_EXT_ANEG_LOCAL_EEEADV 0x3C +#define ANEG_LOCA_EEEADV_100BT 0x0002 +#define ANEG_LOCA_EEEADV_1000BT 0x0004 + +#define MII_EXT_ANEG_AFE 0x801A +#define ANEG_AFEE_10BT_100M_TH 0x0040 + +#define MII_EXT_ANEG_S3DIG10 0x8023 +#define ANEG_S3DIG10_SL 0x0001 +#define ANEG_S3DIG10_DEFAULT 0 + +#define MII_EXT_ANEG_NLP78 0x8027 +#define ANEG_NLP78_120M_DEFAULT 0x8A05 + /* Statistics counters collected by the MAC. */ struct smb { /* Rx stats. */ @@ -990,7 +1306,10 @@ struct tx_desc { /* Water mark to kick reclaiming Tx buffers. */ #define ALC_TX_DESC_HIWAT ((ALC_TX_RING_CNT * 6) / 10) - +/* + * AR816x controllers support up to 16 messages but this driver + * uses single message. + */ #define ALC_MSI_MESSAGES 1 #define ALC_MSIX_MESSAGES 1 @@ -1160,15 +1479,17 @@ struct alc_softc { #define ALC_FLAG_PM 0x0010 #define ALC_FLAG_FASTETHER 0x0020 #define ALC_FLAG_JUMBO 0x0040 -#define ALC_FLAG_ASPM_MON 0x0080 #define ALC_FLAG_CMB_BUG 0x0100 #define ALC_FLAG_SMB_BUG 0x0200 #define ALC_FLAG_L0S 0x0400 #define ALC_FLAG_L1S 0x0800 #define ALC_FLAG_APS 0x1000 -#define ALC_FLAG_DETACH 0x4000 + +#define ALC_FLAG_AR816X_FAMILY 0x2000 +#define ALC_FLAG_LINK_WAR 0x4000 #define ALC_FLAG_LINK 0x8000 + struct timeout alc_tick_ch; struct alc_hw_stats alc_stats; struct alc_chain_data alc_cdata; @@ -1202,5 +1523,10 @@ do { \ #define ALC_RESET_TIMEOUT 100 #define ALC_TIMEOUT 1000 #define ALC_PHY_TIMEOUT 1000 + + +#define MASTER_WAKEN_25M 0x00000020 +#define ALC_FLAG_MSI 0x0004 +#define ALC_FLAG_MSIX 0x0008 #endif /* _IF_ALCREG_H */
