Thank you for the quick response, and sorry for the delay in the
result (also sorry for top-posting, don't know how to avoid it in
this setting)..
With the patch applied, the interface seems to be working fine
(as it's only a 2-port system, the 2 extra interfaces that are
unable to initialize are expected I guess?). The MAC addresses
are retrieved successfully in the proper dmesg, but I've replaced
the NIC-specific parts with ? in the output below.
Thanks again for the quick reply and patch!
--Paul
===
OpenBSD 5.8-current (GENERIC.MP) #2: Sat Sep 12 01:26:21 CEST 2015
[email protected]:/usr/src/sys/arch/amd64/compile/GENERIC.MP
real mem = 2126372864 (2027MB)
avail mem = 2058027008 (1962MB)
mpath0 at root
scsibus0 at mpath0: 256 targets
mainbus0 at root
bios0 at mainbus0
acpi0 at bios0: rev 2
acpi0: sleep states S0 S4 S5
acpi0: tables DSDT FACP SPCR HPET APIC MCFG SSDT
acpi0: wakeup devices EHC1(S4)
acpitimer0 at acpi0: 3579545 Hz, 24 bits
acpihpet0 at acpi0: 14318179 Hz
acpimadt0 at acpi0 addr 0xfee00000: PC-AT compat
cpu0 at mainbus0: apid 0 (boot processor)
cpu0: Intel(R) Atom(TM) CPU C2338 @ 1.74GHz, 1166.89 MHz
cpu0: FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,
PAT,PSE36,CFLUSH,DS,ACPI,MMX,FXSR,SSE,SSE2,SS,HTT,TM,PBE,SSE3,PCLMUL,
DTES64,MWAIT,DS-CPL,VMX,EST,TM2,SSSE3,CX16,xTPR,PDCM,SSE4.1,SSE4.2,
MOVBE,POPCNT,DEADLINE,AES,RDRAND,NXE,LONG,LAHF,3DNOWP,PERF,ITSC,SMEP,
ERMS,SENSOR,ARAT
cpu0: 1MB 64b/line 16-way L2 cache
cpu0: smt 0, core 0, package 0
mtrr: Pentium Pro MTRR support, 8 var ranges, 88 fixed ranges
cpu0: apic clock running at 83MHz
cpu0: mwait min=64, max=64, C-substates=0.2.0.0.0.0.3, IBE
cpu1 at mainbus0: apid 2 (application processor)
cpu1: Intel(R) Atom(TM) CPU C2338 @ 1.74GHz, 1166.66 MHz
cpu1: FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,
PAT,PSE36,CFLUSH,DS,ACPI,MMX,FXSR,SSE,SSE2,SS,HTT,TM,PBE,SSE3,PCLMUL,
DTES64,MWAIT,DS-CPL,VMX,EST,TM2,SSSE3,CX16,xTPR,PDCM,SSE4.1,SSE4.2,
MOVBE,POPCNT,DEADLINE,AES,RDRAND,NXE,LONG,LAHF,3DNOWP,PERF,ITSC,SMEP,
ERMS,SENSOR,ARAT
cpu1: 1MB 64b/line 16-way L2 cache
cpu1: smt 0, core 1, package 0
ioapic0 at mainbus0: apid 2 pa 0xfec00000, version 20, 24 pins
acpimcfg0 at acpi0 addr 0xe0000000, bus 0-255
acpiprt0 at acpi0: bus 1 (RP01)
acpiprt1 at acpi0: bus 2 (RP02)
acpiprt2 at acpi0: bus 3 (RP03)
acpiprt3 at acpi0: bus 4 (RP04)
acpiprt4 at acpi0: bus 0 (PCI0)
acpicpu0 at acpi0: C1(@1 halt!), PSS
acpicpu1 at acpi0: C1(@1 halt!), PSS
cpu0: Enhanced SpeedStep 1166 MHz: speeds: 2100, 1800, 1600, 1400 MHz
pci0 at mainbus0 bus 0
pchb0 at pci0 dev 0 function 0 vendor "Intel", unknown product 0x1f0f
rev 0x02
ppb0 at pci0 dev 1 function 0 "Intel Atom C2000 PCIE" rev 0x02: msi
pci1 at ppb0 bus 1
ppb1 at pci0 dev 2 function 0 "Intel Atom C2000 PCIE" rev 0x02: msi
pci2 at ppb1 bus 2
ppb2 at pci0 dev 3 function 0 "Intel Atom C2000 PCIE" rev 0x02: msi
pci3 at ppb2 bus 3
ppb3 at pci0 dev 4 function 0 "Intel Atom C2000 PCIE" rev 0x02: msi
pci4 at ppb3 bus 4
pchb1 at pci0 dev 14 function 0 "Intel Atom C2000 RAS" rev 0x02
"Intel Atom C2000 RCEC" rev 0x02 at pci0 dev 15 function 0
not configured
"Intel Atom C2000 SMBus" rev 0x02 at pci0 dev 19 function 0
not configured
em0 at pci0 dev 20 function 0 "Intel I354 SGMII" rev 0x03: msi,
address 00:08:a2:??:??:??
em1 at pci0 dev 20 function 1 "Intel I354 SGMII" rev 0x03: msi,
address 00:08:a2:??:??:??
em2 at pci0 dev 20 function 2 "Intel I354 SGMII" rev 0x03: msiem2:
Hardware Initialization Failedem2: Unable to initialize the hardware
em3 at pci0 dev 20 function 3 "Intel I354 SGMII" rev 0x03: msiem3:
Hardware Initialization Failedem3: Unable to initialize the hardware
ehci0 at pci0 dev 22 function 0 "Intel Atom C2000 USB" rev 0x02:
apic 2 int 22
usb0 at ehci0: USB revision 2.0
uhub0 at usb0 "Intel EHCI root hub" rev 2.00/1.00 addr 1
ahci0 at pci0 dev 23 function 0 "Intel Atom C2000 AHCI" rev 0x02:
msi, AHCI 1.3
scsibus1 at ahci0: 32 targets
ahci1 at pci0 dev 24 function 0 "Intel Atom C2000 AHCI" rev 0x02:
msi, AHCI 1.3
scsibus2 at ahci1: 32 targets
pcib0 at pci0 dev 31 function 0 "Intel Atom C2000 PCU" rev 0x02
ichiic0 at pci0 dev 31 function 3 "Intel Atom C2000 PCU SMBus"
rev 0x02: apic 2 int 22
iic0 at ichiic0
iic0: addr 0x2e 00=3a words 00=3a3a 01=0000 02=0000 03=0000 04=0000
05=0000 06=0000 07=0000
spdmem0 at iic0 addr 0x50: 2GB DDR3 SDRAM PC3-12800
isa0 at pcib0
isadma0 at isa0
com0 at isa0 port 0x3f8/8 irq 4: ns16550a, 16 byte fifo
com1 at isa0 port 0x2f8/8 irq 3: ns16550a, 16 byte fifo
com1: console
pcppi0 at isa0 port 0x61
spkr0 at pcppi0
uhub1 at uhub0 port 1 "Intel product 0x07db" rev 2.00/0.02 addr 2
umass0 at uhub1 port 3 configuration 1 interface 0
"Generic Ultra Fast Media" rev 2.00/1.98 addr 3
umass0: using SCSI over Bulk-Only
scsibus3 at umass0: 2 targets, initiator 0
sd0 at scsibus3 targ 1 lun 0:
SCSI0 0/direct removable serial.04242240000000225001
sd0: 3776MB, 512 bytes/sector, 7733248 sectors
vscsi0 at root
scsibus4 at vscsi0: 256 targets
softraid0 at root
scsibus5 at softraid0: 256 targets
root on sd0a (61e77b28ba8850b3.a) swap on sd0b dump on sd0b
> Date: Wed, 9 Sep 2015 14:37:33 +1000
> From: [email protected]
> To: [email protected]
> CC: [email protected]
> Subject: Re: I354 initialization error on DFF 2220
>
> On Tue, Sep 08, 2015 at 09:38:23PM +0000, Paul Levlin wrote:
>> Trying to install OpenBSD on a Netgate RCC-DFF 2220 system, but
>> it seems like the Intel I354 interface has trouble initializing.
>>
>> I've tried 5.7-release and -current, both show the same output
>> while attempting to initialize.
>>
>> As the I354 is listed in the supported adapters for em(4), I'm
>> hoping it's a simple bug that I'd be happy to verify a fix for.
>>
>> Pointers to how to provide better debug info for the devs
>>
>> in this case (if needed) are also appreciated.
>>
>> If I'm barking up the wrong tree, I'd be happy for a reality check
>> too..
>
> em supports the I354 mac but not every phy that can be hooked
> up to it. It seems likely that the 88E1514 phys in that board
> have the same ids as the 88E1512 phy. In which case the following
> may help:
>
> Index: if_em_hw.c
> ===================================================================
> RCS file: /cvs/src/sys/dev/pci/if_em_hw.c,v
> retrieving revision 1.87
> diff -u -p -r1.87 if_em_hw.c
> --- if_em_hw.c 5 Aug 2015 18:31:14 -0000 1.87
> +++ if_em_hw.c 9 Sep 2015 04:29:33 -0000
> @@ -182,7 +182,7 @@ int32_t em_get_pcs_speed_and_duplex_825
> int32_t em_set_eee_i350(struct em_hw *);
> int32_t em_set_eee_pchlan(struct em_hw *);
> int32_t em_valid_nvm_bank_detect_ich8lan(struct em_hw *, uint32_t *);
> -
> +int32_t em_initialize_M88E1512_phy(struct em_hw *);
>
> /* IGP cable length table */
> static const uint16_t
> @@ -229,6 +229,7 @@ em_set_phy_type(struct em_hw *hw)
> case M88E1111_I_PHY_ID:
> case M88E1112_E_PHY_ID:
> case M88E1543_E_PHY_ID:
> + case M88E1512_E_PHY_ID:
> case I210_I_PHY_ID:
> case I347AT4_E_PHY_ID:
> hw->phy_type = em_phy_m88;
> @@ -5272,6 +5273,12 @@ em_phy_reset(struct em_hw *hw)
> em_gate_hw_phy_config_ich8lan(hw, FALSE);
> }
>
> + if (hw->phy_id == M88E1512_E_PHY_ID) {
> + ret_val = em_initialize_M88E1512_phy(hw);
> + if (ret_val)
> + return ret_val;
> + }
> +
> return E1000_SUCCESS;
> }
>
> @@ -5410,7 +5417,8 @@ em_match_gig_phy(struct em_hw *hw)
> hw->phy_id == I347AT4_E_PHY_ID ||
> hw->phy_id == I350_I_PHY_ID ||
> hw->phy_id == M88E1112_E_PHY_ID ||
> - hw->phy_id == M88E1543_E_PHY_ID) {
> + hw->phy_id == M88E1543_E_PHY_ID ||
> + hw->phy_id == M88E1512_E_PHY_ID) {
> uint32_t mdic;
>
> mdic = EM_READ_REG(hw, E1000_MDICNFG);
> @@ -10894,5 +10902,94 @@ em_set_eee_pchlan(struct em_hw *hw)
> ret_val = em_write_phy_reg(hw, I82579_LPI_CTRL, phy_reg);
> out:
> return ret_val;
> +}
> +
> +/**
> + * em_initialize_M88E1512_phy - Initialize M88E1512 PHY
> + * @hw: pointer to the HW structure
> + *
> + * Initialize Marvell 1512 to work correctly with Avoton.
> + **/
> +int32_t
> +em_initialize_M88E1512_phy(struct em_hw *hw)
> +{
> + int32_t ret_val = E1000_SUCCESS;
> +
> + DEBUGFUNC("e1000_initialize_M88E1512_phy");
> +
> + /* Check if this is correct PHY. */
> + if (hw->phy_id != M88E1512_E_PHY_ID)
> + goto out;
> +
> + /* Switch to PHY page 0xFF. */
> + ret_val = em_write_phy_reg(hw, M88E1543_PAGE_ADDR, 0x00FF);
> + if (ret_val)
> + goto out;
> +
> + ret_val = em_write_phy_reg(hw, M88E1512_CFG_REG_2, 0x214B);
> + if (ret_val)
> + goto out;
> +
> + ret_val = em_write_phy_reg(hw, M88E1512_CFG_REG_1, 0x2144);
> + if (ret_val)
> + goto out;
> +
> + ret_val = em_write_phy_reg(hw, M88E1512_CFG_REG_2, 0x0C28);
> + if (ret_val)
> + goto out;
> +
> + ret_val = em_write_phy_reg(hw, M88E1512_CFG_REG_1, 0x2146);
> + if (ret_val)
> + goto out;
> +
> + ret_val = em_write_phy_reg(hw, M88E1512_CFG_REG_2, 0xB233);
> + if (ret_val)
> + goto out;
> +
> + ret_val = em_write_phy_reg(hw, M88E1512_CFG_REG_1, 0x214D);
> + if (ret_val)
> + goto out;
> +
> + ret_val = em_write_phy_reg(hw, M88E1512_CFG_REG_2, 0xCC0C);
> + if (ret_val)
> + goto out;
> +
> + ret_val = em_write_phy_reg(hw, M88E1512_CFG_REG_1, 0x2159);
> + if (ret_val)
> + goto out;
> +
> + /* Switch to PHY page 0xFB. */
> + ret_val = em_write_phy_reg(hw, M88E1543_PAGE_ADDR, 0x00FB);
> + if (ret_val)
> + goto out;
> +
> + ret_val = em_write_phy_reg(hw, M88E1512_CFG_REG_3, 0x000D);
> + if (ret_val)
> + goto out;
> +
> + /* Switch to PHY page 0x12. */
> + ret_val = em_write_phy_reg(hw, M88E1543_PAGE_ADDR, 0x12);
> + if (ret_val)
> + goto out;
> +
> + /* Change mode to SGMII-to-Copper */
> + ret_val = em_write_phy_reg(hw, M88E1512_MODE, 0x8001);
> + if (ret_val)
> + goto out;
> +
> + /* Return the PHY to page 0. */
> + ret_val = em_write_phy_reg(hw, M88E1543_PAGE_ADDR, 0);
> + if (ret_val)
> + goto out;
> +
> + ret_val = em_phy_hw_reset(hw);
> + if (ret_val) {
> + DEBUGOUT("Error committing the PHY changes\n");
> + return ret_val;
> + }
> +
> + msec_delay(1000);
> +out:
> + return ret_val;
> }
>
> Index: if_em_hw.h
> ===================================================================
> RCS file: /cvs/src/sys/dev/pci/if_em_hw.h,v
> retrieving revision 1.66
> diff -u -p -r1.66 if_em_hw.h
> --- if_em_hw.h 5 Aug 2015 18:31:14 -0000 1.66
> +++ if_em_hw.h 9 Sep 2015 04:31:58 -0000
> @@ -2802,6 +2802,15 @@ struct em_host_command_info {
> #define M88E1000_PHY_VCO_REG_BIT8 0x100 /* Bits 8 & 11 are adjusted for */
> #define M88E1000_PHY_VCO_REG_BIT11 0x800 /* improved BER performance */
>
> +#define M88E1543_PAGE_ADDR 0x16 /* Page Offset Register */
> +#define M88E1543_EEE_CTRL_1 0x0
> +#define M88E1543_EEE_CTRL_1_MS 0x0001 /* EEE Master/Slave */
> +
> +#define M88E1512_CFG_REG_1 0x0010
> +#define M88E1512_CFG_REG_2 0x0011
> +#define M88E1512_CFG_REG_3 0x0007
> +#define M88E1512_MODE 0x0014
> +
> /* BME1000 PHY Specific Control Register */
> #define BME1000_PSCR_ENABLE_DOWNSHIFT 0x0800 /* 1 = enable downshift */
> #define BM_PHY_PAGE_SELECT 22 /* Page Select for BM */
> @@ -3424,6 +3433,7 @@ struct em_host_command_info {
> #define I210_I_PHY_ID 0x01410C00
> #define IGP04E1000_E_PHY_ID 0x02A80391
> #define M88E1141_E_PHY_ID 0x01410CD0
> +#define M88E1512_E_PHY_ID 0x01410DD0
>
> /* Bits...
> * 15-5: page
