The patch titled
ppc32: L2 cache prefetch fixes on 745x
has been added to the -mm tree. Its filename is
ppc32-l2-cache-prefetch-fixes-on-745x.patch
Patches currently in -mm which might be from [EMAIL PROTECTED] are
ppc32-remove-board-support-for-adir.patch
ppc32-remove-board-support-for-ash.patch
ppc32-remove-board-support-for-beech.patch
ppc32-remove-defconfig-for-cedar.patch
ppc32-remove-board-support-for-k2.patch
ppc32-remove-board-support-for-mcpn765.patch
ppc32-remove-board-support-for-menf1.patch
ppc32-remove-board-support-for-oak.patch
ppc32-remove-board-support-for-rainier.patch
ppc32-remove-board-support-for-redwood.patch
ppc32-remove-board-support-for-sm850.patch
ppc32-remove-board-support-for-spd823ts.patch
ppc32-remove-board-support-for-pcore.patch
ppc32-added-support-for-the-book-e-style-watchdog-timer.patch
ppc32-add-ppc_sys-descriptions-for-powerquicc-ii-devices.patch
cpm_uart-fix-2nd-serial-port-on-mpc8560-ads.patch
cpm_uart-use-schedule_timeout-instead-of-direct-call-to.patch
cpm_uart-fix-baseaddress-for-smc-1-and-2.patch
ppc32-cleaned-up-global-namespace-of-book-e-watchdog.patch
ppc32-removed-find_namec.patch
ppc32-ppc_sys-system-on-chip-identification-additions.patch
ppc32-add-config_hz.patch
ppc32-added-pci-support-mpc83xx.patch
ppc32-l2-cache-prefetch-fixes-on-745x.patch
From: Kumar Gala <[EMAIL PROTECTED]>
We run into problems if we blindly enable L2 prefetching without checking
that the L2 cache is actually enabled. Additionaly, if we disable the L2
cache we need to ensure that we disable L2 prefetching.
Signed-off-by: Kumar Gala <[EMAIL PROTECTED]>
Signed-off-by: Benjamin Herrenschmidt <[EMAIL PROTECTED]>
Signed-off-by: Andrew Morton <[EMAIL PROTECTED]>
---
arch/ppc/kernel/cpu_setup_6xx.S | 5 ++++-
arch/ppc/kernel/l2cr.S | 29 +++++++++++++++++++++++++++++
2 files changed, 33 insertions(+), 1 deletion(-)
diff -puN arch/ppc/kernel/cpu_setup_6xx.S~ppc32-l2-cache-prefetch-fixes-on-745x
arch/ppc/kernel/cpu_setup_6xx.S
--- devel/arch/ppc/kernel/cpu_setup_6xx.S~ppc32-l2-cache-prefetch-fixes-on-745x
2005-08-30 21:59:01.000000000 -0700
+++ devel-akpm/arch/ppc/kernel/cpu_setup_6xx.S 2005-08-30 21:59:01.000000000
-0700
@@ -249,8 +249,11 @@ END_FTR_SECTION_IFSET(CPU_FTR_NO_DPM)
sync
isync
- /* Enable L2 HW prefetch
+ /* Enable L2 HW prefetch, if L2 is enabled
*/
+ mfspr r3,SPRN_L2CR
+ andis. r3,r3,[EMAIL PROTECTED]
+ beqlr
mfspr r3,SPRN_MSSCR0
ori r3,r3,3
sync
diff -puN arch/ppc/kernel/l2cr.S~ppc32-l2-cache-prefetch-fixes-on-745x
arch/ppc/kernel/l2cr.S
--- devel/arch/ppc/kernel/l2cr.S~ppc32-l2-cache-prefetch-fixes-on-745x
2005-08-30 21:59:01.000000000 -0700
+++ devel-akpm/arch/ppc/kernel/l2cr.S 2005-08-30 21:59:01.000000000 -0700
@@ -156,6 +156,26 @@ END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
The bit moved on the 7450.....
****/
+BEGIN_FTR_SECTION
+ /* Disable L2 prefetch on some 745x and try to ensure
+ * L2 prefetch engines are idle. As explained by errata
+ * text, we can't be sure they are, we just hope very hard
+ * that well be enough (sic !). At least I noticed Apple
+ * doesn't even bother doing the dcbf's here...
+ */
+ mfspr r4,SPRN_MSSCR0
+ rlwinm r4,r4,0,0,29
+ sync
+ mtspr SPRN_MSSCR0,r4
+ sync
+ isync
+ lis r4,[EMAIL PROTECTED]
+ dcbf 0,r4
+ dcbf 0,r4
+ dcbf 0,r4
+ dcbf 0,r4
+END_FTR_SECTION_IFSET(CPU_FTR_SPEC7450)
+
/* TODO: use HW flush assist when available */
lis r4,0x0002
@@ -231,6 +251,15 @@ END_FTR_SECTION_IFSET(CPU_FTR_SPEC7450)
mtspr SPRN_L2CR,r3
sync
+ /* Enable L2 HW prefetch on 744x/745x */
+BEGIN_FTR_SECTION
+ mfspr r3,SPRN_MSSCR0
+ ori r3,r3,3
+ sync
+ mtspr SPRN_MSSCR0,r3
+ sync
+ isync
+END_FTR_SECTION_IFSET(CPU_FTR_SPEC7450)
4:
/* Restore HID0[DPM] to whatever it was before */
_
-
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