Author: zoltan
Date: 2005-09-23 21:25:21 -0400 (Fri, 23 Sep 2005)
New Revision: 50665
Modified:
trunk/mono/mono/mini/ChangeLog
trunk/mono/mono/mini/cpu-amd64.md
trunk/mono/mono/mini/cpu-ia64.md
trunk/mono/mono/mini/inssel-amd64.brg
trunk/mono/mono/mini/inssel-ia64.brg
trunk/mono/mono/mini/mini-amd64.c
trunk/mono/mono/mini/mini-codegen.c
trunk/mono/mono/mini/mini-ia64.c
trunk/mono/mono/mini/regalloc.c
Log:
2005-09-24 Zoltan Varga <[EMAIL PROTECTED]>
* Reapply reverted patches.
Modified: trunk/mono/mono/mini/ChangeLog
===================================================================
--- trunk/mono/mono/mini/ChangeLog 2005-09-24 01:21:18 UTC (rev 50664)
+++ trunk/mono/mono/mini/ChangeLog 2005-09-24 01:25:21 UTC (rev 50665)
@@ -1,5 +1,7 @@
2005-09-24 Zoltan Varga <[EMAIL PROTECTED]>
+ * Reapply reverted patches.
+
* *: Revert r50174 as well.
* mini-amd64.c cpu-amd64.md inssel-amd64.brg: Revert r50170 as well.
Modified: trunk/mono/mono/mini/cpu-amd64.md
===================================================================
--- trunk/mono/mono/mini/cpu-amd64.md 2005-09-24 01:21:18 UTC (rev 50664)
+++ trunk/mono/mono/mini/cpu-amd64.md 2005-09-24 01:25:21 UTC (rev 50665)
@@ -11,7 +11,6 @@
# src1:register describes the first source register of an instruction
# src2:register describes the second source register of an instruction
#
-# register may have the following values:
# i integer register
# b base register (used in address references)
# f floating point register
@@ -32,7 +31,6 @@
#
# clob:spec describe if the instruction clobbers registers or has
special needs
#
-# spec can be one of the following characters:
# c clobbers caller-save registers
# 1 clobbers the first source register
# a EAX is clobbered
@@ -42,7 +40,6 @@
#
# flags:spec describe if the instruction uses or sets the flags (unused)
#
-# spec can be one of the following chars:
# s sets the flags
# u uses the flags
# m uses and modifies the flags
@@ -56,15 +53,9 @@
#
# See the code in mini-x86.c for more details on how the specifiers are used.
#
-nop:
break: len:2
jmp: len:42
-br.s:
-brfalse.s:
-brtrue.s:
br: len:6
-brfalse:
-brtrue:
beq: len:8
bge: len:8
bgt: len:8
@@ -75,23 +66,19 @@
bgt.un: len:8
ble.un: len:8
blt.un: len:8
-switch:
+label:
ldind.i1: dest:i len:8
ldind.u1: dest:i len:8
ldind.i2: dest:i len:8
ldind.u2: dest:i len:8
ldind.i4: dest:i len:9
ldind.u4: dest:i len:8
-ldind.i8:
ldind.i: dest:i len:8
-ldind.r4:
-ldind.r8:
ldind.ref: dest:i len:8
stind.ref: src1:b src2:i
stind.i1: src1:b src2:i
stind.i2: src1:b src2:i
stind.i4: src1:b src2:i
-stind.i8:
stind.r4: dest:f src1:b
stind.r8: dest:f src1:b
add: dest:i src1:i src2:i len:3 clob:1
@@ -117,141 +104,35 @@
conv.r8: dest:f src1:i len:9
conv.u4: dest:i src1:i len:3
conv.u8: dest:i src1:i len:3
-callvirt:
-cpobj:
-ldobj:
-ldstr:
-castclass:
-isinst:
conv.r.un: dest:f src1:i len:8
-unbox:
throw: src1:i len:18
op_rethrow: src1:i len:18
-ldfld:
-ldflda:
-stfld:
-ldsfld:
-ldsflda:
-stsfld:
-stobj:
-conv.ovf.i1.un:
-conv.ovf.i2.un:
conv.ovf.i4.un: dest:i src1:i len:16
-conv.ovf.i8.un:
-conv.ovf.u1.un:
-conv.ovf.u2.un:
conv.ovf.u4.un:
-conv.ovf.u8.un:
-conv.ovf.i.un:
-conv.ovf.u.un:
-box:
-newarr:
-ldlen:
-ldelema:
-ldelem.i1:
-ldelem.u1:
-ldelem.i2:
-ldelem.u2:
-ldelem.i4:
-ldelem.u4:
-ldelem.i8:
-ldelem.i:
-ldelem.r4:
-ldelem.r8:
-ldelem.ref:
-stelem.i:
-stelem.i1:
-stelem.i2:
-stelem.i4:
-stelem.i8:
-stelem.r4:
-stelem.r8:
-stelem.ref:
-conv.ovf.i1:
-conv.ovf.u1:
-conv.ovf.i2:
-conv.ovf.u2:
-conv.ovf.i4:
conv.ovf.u4: dest:i src1:i len:15
-conv.ovf.i8:
-conv.ovf.u8:
-refanyval:
ckfinite: dest:f src1:f len:43
-mkrefany:
-ldtoken:
conv.u2: dest:i src1:i len:4
conv.u1: dest:i src1:i len:4
conv.i: dest:i src1:i len:4
-conv.ovf.i:
-conv.ovf.u:
-add.ovf:
-add.ovf.un:
mul.ovf: dest:i src1:i src2:i clob:1 len:10
# this opcode is handled specially in the code generator
mul.ovf.un: dest:i src1:i src2:i len:18
-sub.ovf:
-sub.ovf.un:
-endfinally:
-leave:
-leave.s:
-stind.i:
conv.u: dest:i src1:i len:4
-prefix7:
-prefix6:
-prefix5:
-prefix4:
-prefix3:
-prefix2:
-prefix1:
-prefixref:
-arglist:
ceq: dest:c len:8
cgt: dest:c len:8
cgt.un: dest:c len:8
clt: dest:c len:8
clt.un: dest:c len:8
-ldftn:
-ldvirtftn:
-ldarg:
-ldarga:
-starg:
-ldloc:
-ldloca:
-stloc:
localloc: dest:i src1:i len:84
-endfilter:
-unaligned.:
-volatile.:
-tail.:
-initobj:
-cpblk:
-initblk:
-sizeof:
-refanytype:
-illegal:
-endmac:
-mono_objaddr:
-mono_ldptr:
-mono_vtaddr:
-mono_newobj:
-mono_retobj:
-load:
-ldaddr:
-store:
-phi:
-rename:
compare: src1:i src2:i len:3
lcompare: src1:i src2:i len:3
icompare: src1:i src2:i len:3
compare_imm: src1:i len:13
icompare_imm: src1:i len:8
fcompare: src1:f src2:f clob:a len:13
-local:
-arg:
oparglist: src1:b len:11
outarg: src1:i len:2
outarg_imm: len:6
-retarg:
setret: dest:a src1:i len:3
setlret: dest:i src1:i src2:i len:5
checkthis: src1:b len:5
@@ -271,15 +152,10 @@
vcall_membase: src1:b len:64 clob:c
call_reg: dest:a src1:i len:64 clob:c
call_membase: dest:a src1:b len:64 clob:c
-trap:
iconst: dest:i len:10
i8const: dest:i len:18
r4const: dest:f len:13
r8const: dest:f len:9
-regvar:
-reg:
-regoffset:
-label:
store_membase_imm: dest:b len:15
store_membase_reg: dest:b src1:i len:9
storei8_membase_reg: dest:b src1:i len:9
@@ -306,7 +182,6 @@
loadu4_mem: dest:i len:10
amd64_loadi8_memindex: dest:i src1:i src2:i len:10
move: dest:i src1:i len:4
-setreg: dest:i src1:i len:4
add_imm: dest:i src1:i len:8 clob:1
sub_imm: dest:i src1:i len:8 clob:1
mul_imm: dest:i src1:i len:8
@@ -339,81 +214,24 @@
cond_exc_nc: len:8
cond_exc_iov: len:8
cond_exc_ic: len:8
-long_add:
-long_sub:
long_mul: dest:i src1:i src2:i clob:1 len:4
long_mul_imm: dest:i src1:i src2:i clob:1 len:8
long_div: dest:a src1:a src2:i len:16 clob:d
long_div_un: dest:a src1:a src2:i len:16 clob:d
long_rem: dest:d src1:a src2:i len:16 clob:a
long_rem_un: dest:d src1:a src2:i len:16 clob:a
-long_and:
-long_or:
-long_xor:
long_shl: dest:i src1:i src2:s clob:1 len:31
long_shr: dest:i src1:i src2:s clob:1 len:32
long_shr_un: dest:i src1:i src2:s clob:1 len:32
-long_neg:
-long_not:
-long_conv_to_i1:
-long_conv_to_i2:
-long_conv_to_i4:
-long_conv_to_i8:
long_conv_to_r4: dest:f src1:i len:8
long_conv_to_r8: dest:f src1:i len:8
-long_conv_to_u4:
-long_conv_to_u8:
-long_conv_to_u2:
-long_conv_to_u1:
-long_conv_to_i:
long_conv_to_ovf_i: dest:i src1:i src2:i len:40
-long_conv_to_ovf_u:
-long_add_ovf:
-long_add_ovf_un:
long_mul_ovf: dest:i src1:i src2:i clob:1 len:16
long_mul_ovf_un: dest:i src1:i src2:i len:22
-long_sub_ovf:
-long_sub_ovf_un:
-long_conv_to_ovf_i1_un:
-long_conv_to_ovf_i2_un:
-long_conv_to_ovf_i4_un:
-long_conv_to_ovf_i8_un:
-long_conv_to_ovf_u1_un:
-long_conv_to_ovf_u2_un:
-long_conv_to_ovf_u4_un:
-long_conv_to_ovf_u8_un:
-long_conv_to_ovf_i_un:
-long_conv_to_ovf_u_un:
-long_conv_to_ovf_i1:
-long_conv_to_ovf_u1:
-long_conv_to_ovf_i2:
-long_conv_to_ovf_u2:
-long_conv_to_ovf_i4:
-long_conv_to_ovf_u4:
-long_conv_to_ovf_i8:
-long_conv_to_ovf_u8:
-long_ceq:
-long_cgt:
-long_cgt_un:
-long_clt:
-long_clt_un:
long_conv_to_r_un: dest:f src1:i src2:i len:48
-long_conv_to_u:
long_shr_imm: dest:i src1:i clob:1 len:11
long_shr_un_imm: dest:i src1:i clob:1 len:11
long_shl_imm: dest:i src1:i clob:1 len:11
-long_add_imm:
-long_sub_imm:
-long_beq:
-long_bne_un:
-long_blt:
-long_blt_un:
-long_bgt:
-long_btg_un:
-long_bge:
-long_bge_un:
-long_ble:
-long_ble_un:
float_beq: len:13
float_bne_un: len:18
float_blt: len:13
@@ -437,8 +255,6 @@
float_conv_to_i2: dest:i src1:f len:49
float_conv_to_i4: dest:i src1:f len:49
float_conv_to_i8: dest:i src1:f len:49
-float_conv_to_r4:
-float_conv_to_r8:
float_conv_to_u4: dest:i src1:f len:49
float_conv_to_u8: dest:i src1:f len:49
float_conv_to_u2: dest:i src1:f len:49
@@ -446,30 +262,7 @@
float_conv_to_i: dest:i src1:f len:49
float_conv_to_ovf_i: dest:a src1:f len:40
float_conv_to_ovd_u: dest:a src1:f len:40
-float_add_ovf:
-float_add_ovf_un:
float_mul_ovf:
-float_mul_ovf_un:
-float_sub_ovf:
-float_sub_ovf_un:
-float_conv_to_ovf_i1_un:
-float_conv_to_ovf_i2_un:
-float_conv_to_ovf_i4_un:
-float_conv_to_ovf_i8_un:
-float_conv_to_ovf_u1_un:
-float_conv_to_ovf_u2_un:
-float_conv_to_ovf_u4_un:
-float_conv_to_ovf_u8_un:
-float_conv_to_ovf_i_un:
-float_conv_to_ovf_u_un:
-float_conv_to_ovf_i1:
-float_conv_to_ovf_u1:
-float_conv_to_ovf_i2:
-float_conv_to_ovf_u2:
-float_conv_to_ovf_i4:
-float_conv_to_ovf_u4:
-float_conv_to_ovf_i8:
-float_conv_to_ovf_u8:
float_ceq: dest:i src1:f src2:f len:35
float_cgt: dest:i src1:f src2:f len:35
float_cgt_un: dest:i src1:f src2:f len:48
Modified: trunk/mono/mono/mini/cpu-ia64.md
===================================================================
--- trunk/mono/mono/mini/cpu-ia64.md 2005-09-24 01:21:18 UTC (rev 50664)
+++ trunk/mono/mono/mini/cpu-ia64.md 2005-09-24 01:25:21 UTC (rev 50665)
@@ -4,9 +4,15 @@
# since there are no short branches.
#
+nop:
break: len:48
jmp: len:48
+br.s:
+brfalse.s:
+brtrue.s:
br: len:48
+brfalse:
+brtrue:
beq: len:48
bge: len:48
bgt: len:48
@@ -17,7 +23,7 @@
bgt.un: len:48
ble.un: len:48
blt.un: len:48
-label:
+switch:
add: dest:i src1:i src2:i len:48
sub: dest:i src1:i src2:i len:48
mul: dest:i src1:i src2:i len:48
@@ -41,35 +47,139 @@
conv.r8: dest:f src1:i len:112
conv.u4: dest:i src1:i len:112
conv.u8: dest:i src1:i len:112
+callvirt:
+cpobj:
+ldobj:
+ldstr:
+castclass:
+isinst:
conv.r.un: dest:f src1:i len:48
+unbox:
throw: src1:i len:96
op_rethrow: src1:i len:48
+ldfld:
+ldflda:
+stfld:
+ldsfld:
+ldsflda:
+stsfld:
+stobj:
+conv.ovf.i1.un:
+conv.ovf.i2.un:
conv.ovf.i4.un: dest:i src1:i len:96
+conv.ovf.i8.un:
+conv.ovf.u1.un:
+conv.ovf.u2.un:
conv.ovf.u4.un:
+conv.ovf.u8.un:
+conv.ovf.i.un:
+conv.ovf.u.un:
+box:
+newarr:
+ldlen:
+ldelema:
+ldelem.i1:
+ldelem.u1:
+ldelem.i2:
+ldelem.u2:
+ldelem.i4:
+ldelem.u4:
+ldelem.i8:
+ldelem.i:
+ldelem.r4:
+ldelem.r8:
+ldelem.ref:
+stelem.i:
+stelem.i1:
+stelem.i2:
+stelem.i4:
+stelem.i8:
+stelem.r4:
+stelem.r8:
+stelem.ref:
+conv.ovf.i1:
+conv.ovf.u1:
+conv.ovf.i2:
+conv.ovf.u2:
+conv.ovf.i4:
conv.ovf.u4: dest:i src1:i len:48
+conv.ovf.i8:
+conv.ovf.u8:
+refanyval:
ckfinite: dest:f src1:f len:48
+mkrefany:
+ldtoken:
conv.u2: dest:i src1:i len:48
conv.u1: dest:i src1:i len:48
conv.i: dest:i src1:i len:48
+conv.ovf.i:
+conv.ovf.u:
+add.ovf:
+add.ovf.un:
mul.ovf: dest:i src1:i src2:i len:48
# this opcode is handled specially in the code generator
mul.ovf.un: dest:i src1:i src2:i len:48
+sub.ovf:
+sub.ovf.un:
+leave:
+leave.s:
+stind.i:
conv.u: dest:i src1:i len:48
+prefix7:
+prefix6:
+prefix5:
+prefix4:
+prefix3:
+prefix2:
+prefix1:
+prefixref:
+arglist:
ceq: dest:c len:48
cgt: dest:c len:48
cgt.un: dest:c len:48
clt: dest:c len:48
clt.un: dest:c len:48
+ldftn:
+ldvirtftn:
+ldarg:
+ldarga:
+starg:
+ldloc:
+ldloca:
+stloc:
localloc: dest:i src1:i len:92
+unaligned.:
+volatile.:
+tail.:
+initobj:
+cpblk:
+initblk:
+sizeof:
+refanytype:
+illegal:
+endmac:
+mono_objaddr:
+mono_ldptr:
+mono_vtaddr:
+mono_newobj:
+mono_retobj:
+load:
+ldaddr:
+store:
+phi:
+rename:
compare: src1:i src2:i len:48
lcompare: src1:i src2:i len:48
icompare: src1:i src2:i len:48
compare_imm: src1:i len:48
icompare_imm: src1:i len:48
fcompare: src1:f src2:f clob:a len:48
+local:
+arg:
oparglist: src1:b len:48
outarg: src1:i len:48
outarg_imm: len:48
+retarg:
setret: dest:r src1:i len:48
setlret: dest:r src1:i src2:i len:48
checkthis: src1:b len:48
@@ -92,6 +202,7 @@
i8const: dest:i len:48
r4const: dest:f len:48
r8const: dest:f len:48
+label:
store_membase_imm: dest:b len:48
store_membase_reg: dest:b src1:i len:48
storei8_membase_reg: dest:b src1:i len:48
@@ -117,6 +228,7 @@
loadr8_spill_membase: src1:b len:48
loadu4_mem: dest:i len:48
move: dest:i src1:i len:48
+setreg: dest:i src1:i len:48
add_imm: dest:i src1:i len:48
sub_imm: dest:i src1:i len:48
mul_imm: dest:i src1:i len:48
@@ -163,10 +275,26 @@
long_conv_to_ovf_i: dest:i src1:i src2:i len:48
long_mul_ovf: dest:i src1:i src2:i len:48
long_mul_ovf_un: dest:i src1:i src2:i len:48
+long_ceq:
+long_cgt:
+long_cgt_un:
+long_clt:
+long_clt_un:
long_conv_to_r_un: dest:f src1:i src2:i len:48
+long_conv_to_u:
long_shr_imm: dest:i src1:i len:48
long_shr_un_imm: dest:i src1:i len:48
long_shl_imm: dest:i src1:i len:48
+long_beq:
+long_bne_un:
+long_blt:
+long_blt_un:
+long_bgt:
+long_btg_un:
+long_bge:
+long_bge_un:
+long_ble:
+long_ble_un:
float_beq: len:48
float_bne_un: len:48
float_blt: len:48
@@ -199,7 +327,30 @@
float_conv_to_i: dest:i src1:f len:112
float_conv_to_ovf_i: dest:a src1:f len:112
float_conv_to_ovd_u: dest:a src1:f len:112
+float_add_ovf:
+float_add_ovf_un:
float_mul_ovf:
+float_mul_ovf_un:
+float_sub_ovf:
+float_sub_ovf_un:
+float_conv_to_ovf_i1_un:
+float_conv_to_ovf_i2_un:
+float_conv_to_ovf_i4_un:
+float_conv_to_ovf_i8_un:
+float_conv_to_ovf_u1_un:
+float_conv_to_ovf_u2_un:
+float_conv_to_ovf_u4_un:
+float_conv_to_ovf_u8_un:
+float_conv_to_ovf_i_un:
+float_conv_to_ovf_u_un:
+float_conv_to_ovf_i1:
+float_conv_to_ovf_u1:
+float_conv_to_ovf_i2:
+float_conv_to_ovf_u2:
+float_conv_to_ovf_i4:
+float_conv_to_ovf_u4:
+float_conv_to_ovf_i8:
+float_conv_to_ovf_u8:
float_ceq: dest:i src1:f src2:f len:48
float_cgt: dest:i src1:f src2:f len:48
float_cgt_un: dest:i src1:f src2:f len:48
Modified: trunk/mono/mono/mini/inssel-amd64.brg
===================================================================
--- trunk/mono/mono/mini/inssel-amd64.brg 2005-09-24 01:21:18 UTC (rev
50664)
+++ trunk/mono/mono/mini/inssel-amd64.brg 2005-09-24 01:25:21 UTC (rev
50665)
@@ -204,7 +204,7 @@
stmt: OP_OUTARG_REG (reg) {
MonoCallInst *call = (MonoCallInst*)tree->inst_right;
- tree->opcode = OP_SETREG;
+ tree->opcode = OP_MOVE;
tree->sreg1 = state->left->reg1;
tree->dreg = mono_regstate_next_int (s->rs);
mono_bblock_add_inst (s->cbb, tree);
@@ -212,53 +212,6 @@
mono_call_inst_add_outarg_reg (call, tree->dreg, tree->unused, FALSE);
}
-stmt: OP_OUTARG_REG (CEE_LDIND_I (base)),
-stmt: OP_OUTARG_REG (CEE_LDIND_REF (base)),
-stmt: OP_OUTARG_REG (CEE_LDIND_I1 (base)),
-stmt: OP_OUTARG_REG (CEE_LDIND_U1 (base)),
-stmt: OP_OUTARG_REG (CEE_LDIND_I2 (base)),
-stmt: OP_OUTARG_REG (CEE_LDIND_U2 (base)),
-stmt: OP_OUTARG_REG (CEE_LDIND_I4 (base)),
-stmt: OP_OUTARG_REG (CEE_LDIND_U4 (base)),
-stmt: OP_OUTARG_REG (CEE_LDIND_I8 (base)) {
- MonoCallInst *call = (MonoCallInst*)tree->inst_right;
- guint32 dreg;
- MonoInst *base = state->left->left->tree;
-
- dreg = mono_regstate_next_int (s->rs);
- MONO_EMIT_LOAD_MEMBASE_OP (s, tree, ldind_to_load_membase
(state->left->tree->opcode),
- dreg, base->inst_basereg,
base->inst_offset);
-
- mono_call_inst_add_outarg_reg (call, tree->dreg, tree->unused, FALSE);
-}
-
-stmt: OP_OUTARG_REG (OP_I8CONST),
-stmt: OP_OUTARG_REG (OP_ICONST) {
- MonoCallInst *call = (MonoCallInst*)tree->inst_right;
-
- tree->opcode = OP_ICONST;
- tree->inst_c0 = state->left->tree->inst_c0;
- tree->dreg = mono_regstate_next_int (s->rs);
- mono_bblock_add_inst (s->cbb, tree);
-
- mono_call_inst_add_outarg_reg (call, tree->dreg, tree->unused, FALSE);
-}
-
-stmt: OP_OUTARG_REG (CEE_LDIND_I (OP_REGVAR)),
-stmt: OP_OUTARG_REG (CEE_LDIND_I8 (OP_REGVAR)),
-stmt: OP_OUTARG_REG (CEE_LDIND_I4 (OP_REGVAR)),
-stmt: OP_OUTARG_REG (CEE_LDIND_U4 (OP_REGVAR)),
-stmt: OP_OUTARG_REG (CEE_LDIND_REF (OP_REGVAR)) {
- MonoCallInst *call = (MonoCallInst*)tree->inst_right;
-
- tree->opcode = OP_SETREG;
- tree->sreg1 = state->left->left->tree->dreg;
- tree->dreg = mono_regstate_next_int (s->rs);
- mono_bblock_add_inst (s->cbb, tree);
-
- mono_call_inst_add_outarg_reg (call, tree->dreg, tree->unused, FALSE);
-}
-
# we need to reduce this code duplication with some burg syntax extension
stmt: OP_OUTARG (CEE_LDIND_REF (OP_REGVAR)) {
tree->opcode = OP_X86_PUSH;
Modified: trunk/mono/mono/mini/inssel-ia64.brg
===================================================================
--- trunk/mono/mono/mini/inssel-ia64.brg 2005-09-24 01:21:18 UTC (rev
50664)
+++ trunk/mono/mono/mini/inssel-ia64.brg 2005-09-24 01:25:21 UTC (rev
50665)
@@ -138,6 +138,55 @@
mono_call_inst_add_outarg_reg (call, tree->dreg, tree->unused, FALSE);
}
+stmt: OP_OUTARG_REG (CEE_LDIND_I (base)),
+stmt: OP_OUTARG_REG (CEE_LDIND_REF (base)),
+stmt: OP_OUTARG_REG (CEE_LDIND_I1 (base)),
+stmt: OP_OUTARG_REG (CEE_LDIND_U1 (base)),
+stmt: OP_OUTARG_REG (CEE_LDIND_I2 (base)),
+stmt: OP_OUTARG_REG (CEE_LDIND_U2 (base)),
+stmt: OP_OUTARG_REG (CEE_LDIND_I4 (base)),
+stmt: OP_OUTARG_REG (CEE_LDIND_U4 (base)),
+stmt: OP_OUTARG_REG (CEE_LDIND_I8 (base)) {
+ /* FIXME: Move this to inssel.brg or inssel-long.brg */
+ MonoCallInst *call = (MonoCallInst*)tree->inst_right;
+ guint32 dreg;
+ MonoInst *base = state->left->left->tree;
+
+ dreg = mono_regstate_next_int (s->rs);
+ MONO_EMIT_LOAD_MEMBASE_OP (s, tree, ldind_to_load_membase
(state->left->tree->opcode),
+ dreg, base->inst_basereg,
base->inst_offset);
+
+ mono_call_inst_add_outarg_reg (call, tree->dreg, tree->unused, FALSE);
+}
+
+stmt: OP_OUTARG_REG (OP_I8CONST),
+stmt: OP_OUTARG_REG (OP_ICONST) {
+ /* FIXME: Move this to inssel.brg or inssel-long.brg */
+ MonoCallInst *call = (MonoCallInst*)tree->inst_right;
+
+ tree->opcode = OP_ICONST;
+ tree->inst_c0 = state->left->tree->inst_c0;
+ tree->dreg = mono_regstate_next_int (s->rs);
+ mono_bblock_add_inst (s->cbb, tree);
+
+ mono_call_inst_add_outarg_reg (call, tree->dreg, tree->unused, FALSE);
+}
+
+stmt: OP_OUTARG_REG (CEE_LDIND_I (OP_REGVAR)),
+stmt: OP_OUTARG_REG (CEE_LDIND_I8 (OP_REGVAR)),
+stmt: OP_OUTARG_REG (CEE_LDIND_I4 (OP_REGVAR)),
+stmt: OP_OUTARG_REG (CEE_LDIND_U4 (OP_REGVAR)),
+stmt: OP_OUTARG_REG (CEE_LDIND_REF (OP_REGVAR)) {
+ MonoCallInst *call = (MonoCallInst*)tree->inst_right;
+
+ tree->opcode = OP_MOVE;
+ tree->sreg1 = state->left->left->tree->dreg;
+ tree->dreg = mono_regstate_next_int (s->rs);
+ mono_bblock_add_inst (s->cbb, tree);
+
+ mono_call_inst_add_outarg_reg (call, tree->dreg, tree->unused, FALSE);
+}
+
stmt: OP_OUTARG_FREG (freg) {
MonoCallInst *call = (MonoCallInst*)tree->inst_right;
Modified: trunk/mono/mono/mini/mini-amd64.c
===================================================================
--- trunk/mono/mono/mini/mini-amd64.c 2005-09-24 01:21:18 UTC (rev 50664)
+++ trunk/mono/mono/mini/mini-amd64.c 2005-09-24 01:25:21 UTC (rev 50665)
@@ -1331,7 +1331,7 @@
}
/* FIXME: Add more instructions */
-#define INST_IGNORES_CFLAGS(ins) (((ins)->opcode == CEE_BR) || ((ins)->opcode
== OP_STORE_MEMBASE_IMM) || ((ins)->opcode == OP_STOREI8_MEMBASE_REG) ||
((ins)->opcode == OP_MOVE) || ((ins)->opcode == OP_SETREG) || ((ins)->opcode ==
OP_ICONST) || ((ins)->opcode == OP_I8CONST) || ((ins)->opcode ==
OP_LOAD_MEMBASE))
+#define INST_IGNORES_CFLAGS(ins) (((ins)->opcode == CEE_BR) || ((ins)->opcode
== OP_STORE_MEMBASE_IMM) || ((ins)->opcode == OP_STOREI8_MEMBASE_REG) ||
((ins)->opcode == OP_MOVE) || ((ins)->opcode == OP_ICONST) || ((ins)->opcode ==
OP_I8CONST) || ((ins)->opcode == OP_LOAD_MEMBASE))
static void
peephole_pass (MonoCompile *cfg, MonoBasicBlock *bb)
@@ -1522,7 +1522,6 @@
case CEE_CONV_I4:
case CEE_CONV_U4:
case OP_MOVE:
- case OP_SETREG:
/*
* Removes:
*
@@ -2525,7 +2524,6 @@
case CEE_CONV_I4:
case CEE_CONV_U4:
case OP_MOVE:
- case OP_SETREG:
amd64_mov_reg_reg (code, ins->dreg, ins->sreg1, sizeof
(gpointer));
break;
case OP_AMD64_SET_XMMREG_R4: {
@@ -4562,10 +4560,9 @@
mono_arch_emit_this_vret_args (MonoCompile *cfg, MonoCallInst *inst, int
this_reg, int this_type, int vt_reg)
{
MonoCallInst *call = (MonoCallInst*)inst;
- int out_reg = param_regs [0];
+ CallInfo * cinfo = get_call_info (inst->signature, FALSE);
if (vt_reg != -1) {
- CallInfo * cinfo = get_call_info (inst->signature, FALSE);
MonoInst *vtarg;
if (cinfo->ret.storage == ArgValuetypeInReg) {
@@ -4582,30 +4579,28 @@
MONO_EMIT_NEW_BIALU_IMM (cfg, OP_SUB_IMM, X86_ESP,
X86_ESP, 8);
}
else {
- MONO_INST_NEW (cfg, vtarg, OP_SETREG);
+ MONO_INST_NEW (cfg, vtarg, OP_MOVE);
vtarg->sreg1 = vt_reg;
vtarg->dreg = mono_regstate_next_int (cfg->rs);
mono_bblock_add_inst (cfg->cbb, vtarg);
- mono_call_inst_add_outarg_reg (call, vtarg->dreg,
out_reg, FALSE);
-
- out_reg = param_regs [1];
+ mono_call_inst_add_outarg_reg (call, vtarg->dreg,
cinfo->ret.reg, FALSE);
}
-
- g_free (cinfo);
}
/* add the this argument */
if (this_reg != -1) {
MonoInst *this;
- MONO_INST_NEW (cfg, this, OP_SETREG);
+ MONO_INST_NEW (cfg, this, OP_MOVE);
this->type = this_type;
this->sreg1 = this_reg;
this->dreg = mono_regstate_next_int (cfg->rs);
mono_bblock_add_inst (cfg->cbb, this);
- mono_call_inst_add_outarg_reg (call, this->dreg, out_reg,
FALSE);
+ mono_call_inst_add_outarg_reg (call, this->dreg, cinfo->args
[0].reg, FALSE);
}
+
+ g_free (cinfo);
}
MonoInst*
Modified: trunk/mono/mono/mini/mini-codegen.c
===================================================================
--- trunk/mono/mono/mini/mini-codegen.c 2005-09-24 01:21:18 UTC (rev 50664)
+++ trunk/mono/mono/mini/mini-codegen.c 2005-09-24 01:25:21 UTC (rev 50665)
@@ -177,12 +177,14 @@
return load;
}
+#define regmask(reg) (((regmask_t)1) << (reg))
+
#define is_hard_ireg(r) ((r) >= 0 && (r) < MONO_MAX_IREGS)
#define is_hard_freg(r) ((r) >= 0 && (r) < MONO_MAX_FREGS)
-#define is_global_ireg(r) (is_hard_ireg ((r)) && (MONO_ARCH_CALLEE_SAVED_REGS
& (1 << (r))))
-#define is_local_ireg(r) (is_hard_ireg ((r)) && (MONO_ARCH_CALLEE_REGS & (1 <<
(r))))
-#define is_global_freg(r) (is_hard_freg ((r)) && (MONO_ARCH_CALLEE_SAVED_FREGS
& (1 << (r))))
-#define is_local_freg(r) (is_hard_ireg ((r)) && (MONO_ARCH_CALLEE_FREGS & (1
<< (r))))
+#define is_global_ireg(r) (is_hard_ireg ((r)) && (MONO_ARCH_CALLEE_SAVED_REGS
& (regmask (r))))
+#define is_local_ireg(r) (is_hard_ireg ((r)) && (MONO_ARCH_CALLEE_REGS &
(regmask (r))))
+#define is_global_freg(r) (is_hard_freg ((r)) && (MONO_ARCH_CALLEE_SAVED_FREGS
& (regmask (r))))
+#define is_local_freg(r) (is_hard_ireg ((r)) && (MONO_ARCH_CALLEE_FREGS &
(regmask (r))))
#define ireg_is_freeable(r) is_local_ireg ((r))
#define freg_is_freeable(r) is_hard_freg ((r))
@@ -199,15 +201,20 @@
#define dreg_is_fp(ins) (ins_spec [(ins)->opcode] [MONO_INST_DEST] == 'f')
#endif
-#define regpair_reg2_mask(desc,hreg1) ((MONO_ARCH_INST_REGPAIR_REG2
(desc,hreg1) != -1) ? (1 << MONO_ARCH_INST_REGPAIR_REG2 (desc,hreg1)) :
MONO_ARCH_CALLEE_REGS)
+#define regpair_reg2_mask(desc,hreg1) ((MONO_ARCH_INST_REGPAIR_REG2
(desc,hreg1) != -1) ? (regmask (MONO_ARCH_INST_REGPAIR_REG2 (desc,hreg1))) :
MONO_ARCH_CALLEE_REGS)
+#ifdef MONO_ARCH_IS_GLOBAL_IREG
+#undef is_global_ireg
+#define is_global_ireg(reg) MONO_ARCH_IS_GLOBAL_IREG ((reg))
+#endif
+
typedef struct {
int born_in;
int killed_in;
int last_use;
int prev_use;
int flags; /* used to track fp spill/load */
- guint32 preferred_mask; /* the hreg where the register should be
allocated, or 0 */
+ regmask_t preferred_mask; /* the hreg where the register should be
allocated, or 0 */
} RegTrack;
static void
@@ -342,16 +349,16 @@
ins->next = load;
DEBUG (g_print ("SPILLED LOAD (%d at 0x%08lx(%%ebp)) R%d (freed %s)\n",
spill, (long)load->inst_offset, i, mono_regname_full (sel, fp)));
if (fp)
- i = mono_regstate_alloc_float (cfg->rs, 1 << sel);
+ i = mono_regstate_alloc_float (cfg->rs, regmask (sel));
else
- i = mono_regstate_alloc_int (cfg->rs, 1 << sel);
+ i = mono_regstate_alloc_int (cfg->rs, regmask (sel));
g_assert (i == sel);
return sel;
}
static int
-get_register_spilling (MonoCompile *cfg, InstList *item, MonoInst *ins,
guint32 regmask, int reg, gboolean fp)
+get_register_spilling (MonoCompile *cfg, InstList *item, MonoInst *ins,
regmask_t regmask, int reg, gboolean fp)
{
MonoInst *load;
int i, sel, spill;
@@ -366,34 +373,34 @@
symbolic = cfg->rs->isymbolic;
}
- DEBUG (g_print ("\tstart regmask to assign R%d: 0x%08x (R%d <- R%d
R%d)\n", reg, regmask, ins->dreg, ins->sreg1, ins->sreg2));
+ DEBUG (g_print ("\tstart regmask to assign R%d: 0x%08lx (R%d <- R%d
R%d)\n", reg, (guint64)regmask, ins->dreg, ins->sreg1, ins->sreg2));
/* exclude the registers in the current instruction */
if ((sreg1_is_fp (ins) == fp) && (reg != ins->sreg1) &&
(reg_is_freeable (ins->sreg1, fp) || (is_soft_reg (ins->sreg1, fp) && rassign
(cfg, ins->sreg1, fp) >= 0))) {
if (is_soft_reg (ins->sreg1, fp))
- regmask &= ~ (1 << rassign (cfg, ins->sreg1, fp));
+ regmask &= ~ (regmask (rassign (cfg, ins->sreg1, fp)));
else
- regmask &= ~ (1 << ins->sreg1);
+ regmask &= ~ (regmask (ins->sreg1));
DEBUG (g_print ("\t\texcluding sreg1 %s\n", mono_regname_full
(ins->sreg1, fp)));
}
if ((sreg2_is_fp (ins) == fp) && (reg != ins->sreg2) &&
(reg_is_freeable (ins->sreg2, fp) || (is_soft_reg (ins->sreg2, fp) && rassign
(cfg, ins->sreg2, fp) >= 0))) {
if (is_soft_reg (ins->sreg2, fp))
- regmask &= ~ (1 << rassign (cfg, ins->sreg2, fp));
+ regmask &= ~ (regmask (rassign (cfg, ins->sreg2, fp)));
else
- regmask &= ~ (1 << ins->sreg2);
+ regmask &= ~ (regmask (ins->sreg2));
DEBUG (g_print ("\t\texcluding sreg2 %s %d\n",
mono_regname_full (ins->sreg2, fp), ins->sreg2));
}
if ((dreg_is_fp (ins) == fp) && (reg != ins->dreg) && reg_is_freeable
(ins->dreg, fp)) {
- regmask &= ~ (1 << ins->dreg);
+ regmask &= ~ (regmask (ins->dreg));
DEBUG (g_print ("\t\texcluding dreg %s\n", mono_regname_full
(ins->dreg, fp)));
}
- DEBUG (g_print ("\t\tavailable regmask: 0x%08x\n", regmask));
+ DEBUG (g_print ("\t\tavailable regmask: 0x%08lx\n", (guint64)regmask));
g_assert (regmask); /* need at least a register we can free */
sel = -1;
/* we should track prev_use and spill the register that's farther */
if (fp) {
for (i = 0; i < MONO_MAX_FREGS; ++i) {
- if (regmask & (1 << i)) {
+ if (regmask & (regmask (i))) {
sel = i;
DEBUG (g_print ("\t\tselected register %s has
assignment %d\n", mono_arch_fregname (sel), cfg->rs->fsymbolic [sel]));
break;
@@ -407,7 +414,7 @@
}
else {
for (i = 0; i < MONO_MAX_IREGS; ++i) {
- if (regmask & (1 << i)) {
+ if (regmask & (regmask (i))) {
sel = i;
DEBUG (g_print ("\t\tselected register %s has
assignment %d\n", mono_arch_regname (sel), cfg->rs->isymbolic [sel]));
break;
@@ -433,9 +440,9 @@
ins->next = load;
DEBUG (g_print ("\tSPILLED LOAD (%d at 0x%08lx(%%ebp)) R%d (freed
%s)\n", spill, (long)load->inst_offset, i, mono_regname_full (sel, fp)));
if (fp)
- i = mono_regstate_alloc_float (cfg->rs, 1 << sel);
+ i = mono_regstate_alloc_float (cfg->rs, regmask (sel));
else
- i = mono_regstate_alloc_int (cfg->rs, 1 << sel);
+ i = mono_regstate_alloc_int (cfg->rs, regmask (sel));
g_assert (i == sel);
return sel;
@@ -444,7 +451,7 @@
static void
free_up_ireg (MonoCompile *cfg, InstList *item, MonoInst *ins, int hreg)
{
- if (!(cfg->rs->ifree_mask & (1 << hreg))) {
+ if (!(cfg->rs->ifree_mask & (regmask (hreg)))) {
DEBUG (g_print ("\tforced spill of R%d\n", cfg->rs->isymbolic
[hreg]));
get_register_force_spilling (cfg, item, ins, cfg->rs->isymbolic
[hreg], FALSE);
mono_regstate_free_int (cfg->rs, hreg);
@@ -455,14 +462,14 @@
free_up_reg (MonoCompile *cfg, InstList *item, MonoInst *ins, int hreg,
gboolean fp)
{
if (fp) {
- if (!(cfg->rs->ffree_mask & (1 << hreg))) {
+ if (!(cfg->rs->ffree_mask & (regmask (hreg)))) {
DEBUG (g_print ("\tforced spill of R%d\n",
cfg->rs->isymbolic [hreg]));
get_register_force_spilling (cfg, item, ins,
cfg->rs->isymbolic [hreg], fp);
mono_regstate_free_float (cfg->rs, hreg);
}
}
else {
- if (!(cfg->rs->ifree_mask & (1 << hreg))) {
+ if (!(cfg->rs->ifree_mask & (regmask (hreg)))) {
DEBUG (g_print ("\tforced spill of R%d\n",
cfg->rs->isymbolic [hreg]));
get_register_force_spilling (cfg, item, ins,
cfg->rs->isymbolic [hreg], fp);
mono_regstate_free_int (cfg->rs, hreg);
@@ -531,13 +538,13 @@
/* flags used in reginfo->flags */
enum {
- MONO_FP_NEEDS_LOAD_SPILL = 1 << 0,
- MONO_FP_NEEDS_SPILL = 1 << 1,
- MONO_FP_NEEDS_LOAD = 1 << 2
+ MONO_FP_NEEDS_LOAD_SPILL = regmask (0),
+ MONO_FP_NEEDS_SPILL = regmask (1),
+ MONO_FP_NEEDS_LOAD = regmask (2)
};
static int
-alloc_int_reg (MonoCompile *cfg, InstList *tmp, MonoInst *ins, guint32
dest_mask, int sym_reg, RegTrack *info)
+alloc_int_reg (MonoCompile *cfg, InstList *tmp, MonoInst *ins, regmask_t
dest_mask, int sym_reg, RegTrack *info)
{
int val;
@@ -557,7 +564,7 @@
}
static int
-alloc_float_reg (MonoCompile *cfg, InstList *tmp, MonoInst *ins, guint32
dest_mask, int sym_reg)
+alloc_float_reg (MonoCompile *cfg, InstList *tmp, MonoInst *ins, regmask_t
dest_mask, int sym_reg)
{
int val;
@@ -571,7 +578,7 @@
}
static int
-alloc_reg (MonoCompile *cfg, InstList *tmp, MonoInst *ins, guint32 dest_mask,
int sym_reg, RegTrack *info, gboolean fp)
+alloc_reg (MonoCompile *cfg, InstList *tmp, MonoInst *ins, regmask_t
dest_mask, int sym_reg, RegTrack *info, gboolean fp)
{
if (fp)
return alloc_float_reg (cfg, tmp, ins, dest_mask, sym_reg);
@@ -580,7 +587,7 @@
}
static inline void
-assign_reg (MonoRegState *rs, int reg, int hreg, gboolean fp)
+assign_reg (MonoCompile *cfg, MonoRegState *rs, int reg, int hreg, gboolean fp)
{
if (fp) {
g_assert (reg >= MONO_MAX_FREGS);
@@ -589,7 +596,7 @@
rs->fassign [reg] = hreg;
rs->fsymbolic [hreg] = reg;
- rs->ffree_mask &= ~ (1 << hreg);
+ rs->ffree_mask &= ~ (regmask (hreg));
}
else {
g_assert (reg >= MONO_MAX_IREGS);
@@ -598,14 +605,14 @@
rs->iassign [reg] = hreg;
rs->isymbolic [hreg] = reg;
- rs->ifree_mask &= ~ (1 << hreg);
+ rs->ifree_mask &= ~ (regmask (hreg));
}
}
static inline void
-assign_ireg (MonoRegState *rs, int reg, int hreg)
+assign_ireg (MonoCompile *cfg, MonoRegState *rs, int reg, int hreg)
{
- assign_reg (rs, reg, hreg, FALSE);
+ assign_reg (cfg, rs, reg, hreg, FALSE);
}
/*
@@ -641,7 +648,7 @@
rs->ffree_mask = MONO_ARCH_CALLEE_FREGS;
if (use_fpstack)
- rs->ffree_mask = 0xff & ~(1 << MONO_ARCH_FPSTACK_SIZE);
+ rs->ffree_mask = 0xff & ~(regmask (MONO_ARCH_FPSTACK_SIZE));
ins = bb->code;
@@ -753,7 +760,7 @@
dest_dreg = MONO_ARCH_INST_FIXED_REG (spec
[MONO_INST_DEST]);
if (dest_dreg != -1)
- reginfod [ins->dreg].preferred_mask = (1 <<
dest_dreg);
+ reginfod [ins->dreg].preferred_mask = (regmask
(dest_dreg));
if (MONO_ARCH_INST_IS_REGPAIR (spec [MONO_INST_DEST])) {
/* The virtual register is allocated
sequentially */
@@ -824,7 +831,7 @@
int prev_dreg, prev_sreg1, prev_sreg2, clob_dreg;
int dest_dreg, dest_sreg1, dest_sreg2, clob_reg;
int dreg_high, sreg1_high;
- guint32 dreg_mask, sreg1_mask, sreg2_mask, mask;
+ regmask_t dreg_mask, sreg1_mask, sreg2_mask, mask;
const unsigned char *ip;
--i;
ins = tmp->data;
@@ -926,7 +933,7 @@
* TRACK FIXED SREG2
*/
if (dest_sreg2 != -1) {
- if (rs->ifree_mask & (1 << dest_sreg2)) {
+ if (rs->ifree_mask & (regmask (dest_sreg2))) {
if (is_global_ireg (ins->sreg2)) {
/* Argument already in hard reg, need
to copy */
MonoInst *copy = create_copy_ins (cfg,
dest_sreg2, ins->sreg2, NULL, ip, FALSE);
@@ -934,13 +941,13 @@
}
else {
DEBUG (g_print ("\tshortcut assignment
of R%d to %s\n", ins->sreg2, mono_arch_regname (dest_sreg2)));
- assign_ireg (rs, ins->sreg2,
dest_sreg2);
+ assign_ireg (cfg, rs, ins->sreg2,
dest_sreg2);
}
} else {
int need_spill = TRUE;
- dreg_mask &= ~ (1 << dest_sreg2);
- sreg1_mask &= ~ (1 << dest_sreg2);
+ dreg_mask &= ~ (regmask (dest_sreg2));
+ sreg1_mask &= ~ (regmask (dest_sreg2));
/*
* First check if dreg is assigned to
dest_sreg2, since we
@@ -959,7 +966,7 @@
DEBUG (g_print ("\tchanging dreg R%d to
%s from %s\n", ins->dreg, mono_arch_regname (new_dest), mono_arch_regname
(dest_sreg2)));
prev_dreg = ins->dreg;
- assign_ireg (rs, ins->dreg, new_dest);
+ assign_ireg (cfg, rs, ins->dreg,
new_dest);
clob_dreg = ins->dreg;
create_copy_ins (cfg, dest_sreg2,
new_dest, ins, ip, FALSE);
need_spill = FALSE;
@@ -989,7 +996,7 @@
if (!is_global_ireg (ins->sreg2))
/* force-set sreg2 */
- assign_ireg (rs, ins->sreg2,
dest_sreg2);
+ assign_ireg (cfg, rs, ins->sreg2,
dest_sreg2);
}
ins->sreg2 = dest_sreg2;
}
@@ -1007,9 +1014,9 @@
* avoid allocating sreg1/sreg2 to the same reg.
*/
if (dest_sreg1 != -1)
- dreg_mask &= ~ (1 << dest_sreg1);
+ dreg_mask &= ~ (regmask (dest_sreg1));
if (dest_sreg2 != -1)
- dreg_mask &= ~ (1 << dest_sreg2);
+ dreg_mask &= ~ (regmask (dest_sreg2));
}
/*
@@ -1036,7 +1043,7 @@
if ((!fp || (fp && !use_fpstack)) && (is_soft_reg (ins->dreg,
fp))) {
if (dest_dreg != -1)
- dreg_mask = (1 << dest_dreg);
+ dreg_mask = (regmask (dest_dreg));
val = rassign (cfg, ins->dreg, fp);
@@ -1047,7 +1054,7 @@
spill = -val -1;
}
val = alloc_reg (cfg, tmp, ins, dreg_mask,
ins->dreg, ®info [ins->dreg], fp);
- assign_reg (rs, ins->dreg, val, fp);
+ assign_reg (cfg, rs, ins->dreg, val, fp);
if (spill)
create_spilled_store (cfg, spill, val,
prev_dreg, ins, fp);
}
@@ -1078,7 +1085,7 @@
create_spilled_store (cfg, spill, val,
reg2, ins, fp);
}
else {
- if (! (mask & (1 << val))) {
+ if (! (mask & (regmask (val)))) {
val = mono_regstate_alloc_int (rs,
mask);
if (val < 0)
val = get_register_spilling
(cfg, tmp, ins, mask, reg2, fp);
@@ -1091,7 +1098,7 @@
}
DEBUG (g_print ("\tassigned dreg-high %s to dest
R%d\n", mono_arch_regname (val), reg2));
- assign_reg (rs, reg2, val, fp);
+ assign_reg (cfg, rs, reg2, val, fp);
dreg_high = val;
ins->unused = val;
@@ -1137,14 +1144,14 @@
* The dest reg is read by the instruction, not
written, so
* avoid allocating sreg1/sreg2 to the same reg.
*/
- sreg1_mask &= ~ (1 << ins->dreg);
- sreg2_mask &= ~ (1 << ins->dreg);
+ sreg1_mask &= ~ (regmask (ins->dreg));
+ sreg2_mask &= ~ (regmask (ins->dreg));
}
/*
* TRACK CLOBBERING
*/
- if ((clob_reg != -1) && (!(rs->ifree_mask & (1 << clob_reg)))) {
+ if ((clob_reg != -1) && (!(rs->ifree_mask & (regmask
(clob_reg))))) {
DEBUG (g_print ("\tforced spill of clobbered reg
R%d\n", rs->isymbolic [clob_reg]));
get_register_force_spilling (cfg, tmp, ins,
rs->isymbolic [clob_reg], FALSE);
mono_regstate_free_int (rs, clob_reg);
@@ -1171,7 +1178,7 @@
dreg2 = -1;
for (j = 0; j < MONO_MAX_IREGS; ++j) {
- s = 1 << j;
+ s = regmask (j);
if ((clob_mask & s) && !(rs->ifree_mask & s) &&
(j != ins->sreg1) && (j != dreg) && (j != dreg2)) {
get_register_force_spilling (cfg, tmp,
ins, rs->isymbolic [j], FALSE);
mono_regstate_free_int (rs, j);
@@ -1186,7 +1193,7 @@
dreg = -1;
for (j = 0; j < MONO_MAX_FREGS; ++j) {
- s = 1 << j;
+ s = regmask (j);
if ((clob_mask & s) && !(rs->ffree_mask
& s) && (j != ins->sreg1) && (j != dreg)) {
get_register_force_spilling
(cfg, tmp, ins, rs->fsymbolic [j], TRUE);
mono_regstate_free_float (rs,
j);
@@ -1222,9 +1229,9 @@
hreg = regpair >> 24;
reg = regpair & 0xffffff;
- assign_reg (rs, reg, hreg, FALSE);
+ assign_reg (cfg, rs, reg, hreg, FALSE);
- sreg1_mask &= ~(1 << hreg);
+ sreg1_mask &= ~(regmask (hreg));
DEBUG (g_print ("\tassigned arg reg %s
to R%d\n", mono_arch_regname (hreg), reg));
@@ -1243,7 +1250,7 @@
hreg = regpair >> 24;
reg = regpair & 0xffffff;
- assign_reg (rs, reg, hreg, TRUE);
+ assign_reg (cfg, rs, reg, hreg, TRUE);
DEBUG (g_print ("\tassigned arg reg %s
to R%d\n", mono_arch_fregname (hreg), reg));
@@ -1265,16 +1272,16 @@
/* To simplify things, we allocate the same
regpair to sreg1 and dreg */
if (dest_sreg1 != -1)
g_assert (dest_sreg1 == ins->dreg);
- val = mono_regstate_alloc_int (rs, 1 <<
ins->dreg);
+ val = mono_regstate_alloc_int (rs, regmask
(ins->dreg));
g_assert (val >= 0);
- assign_reg (rs, ins->sreg1, val, fp);
+ assign_reg (cfg, rs, ins->sreg1, val, fp);
DEBUG (g_print ("\tassigned sreg1-low %s to
R%d\n", mono_regname_full (val, fp), ins->sreg1));
- g_assert ((1 << dreg_high) & regpair_reg2_mask
(spec [MONO_INST_SRC1], ins->dreg));
- val = mono_regstate_alloc_int (rs, 1 <<
dreg_high);
+ g_assert ((regmask (dreg_high)) &
regpair_reg2_mask (spec [MONO_INST_SRC1], ins->dreg));
+ val = mono_regstate_alloc_int (rs, regmask
(dreg_high));
g_assert (val >= 0);
- assign_reg (rs, ins->sreg1 + 1, val, fp);
+ assign_reg (cfg, rs, ins->sreg1 + 1, val, fp);
DEBUG (g_print ("\tassigned sreg1-high %s to
R%d\n", mono_regname_full (val, fp), ins->sreg1 + 1));
@@ -1283,9 +1290,9 @@
}
if (dest_sreg1 != -1) {
- sreg1_mask = 1 << dest_sreg1;
+ sreg1_mask = regmask (dest_sreg1);
- if (!(rs->ifree_mask & (1 << dest_sreg1))) {
+ if (!(rs->ifree_mask & (regmask (dest_sreg1))))
{
DEBUG (g_print ("\tforced spill of
R%d\n", rs->isymbolic [dest_sreg1]));
get_register_force_spilling (cfg, tmp,
ins, rs->isymbolic [dest_sreg1], FALSE);
mono_regstate_free_int (rs, dest_sreg1);
@@ -1308,16 +1315,16 @@
spill = -val -1;
}
- if (((ins->opcode == OP_MOVE) ||
(ins->opcode == OP_SETREG)) && !spill && !fp && (!is_global_ireg (ins->dreg) &&
(rs->ifree_mask & (1 << ins->dreg)))) {
+ if (((ins->opcode == OP_MOVE) ||
(ins->opcode == OP_SETREG)) && !spill && !fp && (!is_global_ireg (ins->dreg) &&
(rs->ifree_mask & (regmask (ins->dreg))))) {
/*
* Allocate the same hreg to
sreg1 as well so the
* peephole can get rid of the
move.
*/
- sreg1_mask = 1 << ins->dreg;
+ sreg1_mask = regmask
(ins->dreg);
}
val = alloc_reg (cfg, tmp, ins,
sreg1_mask, ins->sreg1, ®info [ins->sreg1], fp);
- assign_reg (rs, ins->sreg1, val, fp);
+ assign_reg (cfg, rs, ins->sreg1, val,
fp);
DEBUG (g_print ("\tassigned sreg1 %s to
R%d\n", mono_regname_full (val, fp), ins->sreg1));
if (spill) {
@@ -1338,7 +1345,7 @@
else {
prev_sreg1 = -1;
}
- sreg2_mask &= ~(1 << ins->sreg1);
+ sreg2_mask &= ~(regmask (ins->sreg1));
}
/* Handle the case when sreg1 is a regpair but dreg is not */
@@ -1363,7 +1370,7 @@
g_assert_not_reached ();
}
else {
- if (! (mask & (1 << val))) {
+ if (! (mask & (regmask (val)))) {
/* The vreg is already allocated to a
wrong hreg */
/* FIXME: */
g_assert_not_reached ();
@@ -1382,7 +1389,7 @@
sreg1_high = val;
DEBUG (g_print ("\tassigned sreg1 hreg %s to dest
R%d\n", mono_arch_regname (val), reg2));
- assign_reg (rs, reg2, val, fp);
+ assign_reg (cfg, rs, reg2, val, fp);
}
/* Handle dreg==sreg1 */
@@ -1433,10 +1440,10 @@
* Need to prevent sreg2 to be allocated to sreg1,
since that
* would screw up the previous copy.
*/
- sreg2_mask &= ~ (1 << ins->sreg1);
+ sreg2_mask &= ~ (regmask (ins->sreg1));
/* we set sreg1 to dest as well */
prev_sreg1 = ins->sreg1 = ins->dreg;
- sreg2_mask &= ~ (1 << ins->dreg);
+ sreg2_mask &= ~ (regmask (ins->dreg));
}
/*
@@ -1455,7 +1462,7 @@
spill = -val -1;
}
val = alloc_reg (cfg, tmp, ins, sreg2_mask,
ins->sreg2, ®info [ins->sreg2], fp);
- assign_reg (rs, ins->sreg2, val, fp);
+ assign_reg (cfg, rs, ins->sreg2, val, fp);
DEBUG (g_print ("\tassigned sreg2 %s to R%d\n",
mono_regname_full (val, fp), ins->sreg2));
if (spill)
create_spilled_store (cfg, spill, val,
prev_sreg2, ins, fp);
Modified: trunk/mono/mono/mini/mini-ia64.c
===================================================================
--- trunk/mono/mono/mini/mini-ia64.c 2005-09-24 01:21:18 UTC (rev 50664)
+++ trunk/mono/mono/mini/mini-ia64.c 2005-09-24 01:25:21 UTC (rev 50665)
@@ -1232,6 +1232,7 @@
switch (ins->opcode) {
case OP_MOVE:
case OP_FMOVE:
+ case OP_SETREG:
/*
* Removes:
*
Modified: trunk/mono/mono/mini/regalloc.c
===================================================================
--- trunk/mono/mono/mini/regalloc.c 2005-09-24 01:21:18 UTC (rev 50664)
+++ trunk/mono/mono/mini/regalloc.c 2005-09-24 01:25:21 UTC (rev 50665)
@@ -60,8 +60,8 @@
int i;
regmask_t mask = allow & rs->ifree_mask;
for (i = 0; i < MONO_MAX_IREGS; ++i) {
- if (mask & (1 << i)) {
- rs->ifree_mask &= ~ (1 << i);
+ if (mask & ((regmask_t)1 << i)) {
+ rs->ifree_mask &= ~ ((regmask_t)1 << i);
rs->max_ireg = MAX (rs->max_ireg, i);
return i;
}
@@ -73,7 +73,7 @@
mono_regstate_free_int (MonoRegState *rs, int reg)
{
if (reg >= 0) {
- rs->ifree_mask |= 1 << reg;
+ rs->ifree_mask |= (regmask_t)1 << reg;
rs->isymbolic [reg] = 0;
}
}
@@ -84,8 +84,8 @@
int i;
regmask_t mask = allow & rs->ffree_mask;
for (i = 0; i < MONO_MAX_FREGS; ++i) {
- if (mask & (1 << i)) {
- rs->ffree_mask &= ~ (1 << i);
+ if (mask & ((regmask_t)1 << i)) {
+ rs->ffree_mask &= ~ ((regmask_t)1 << i);
return i;
}
}
@@ -96,7 +96,7 @@
mono_regstate_free_float (MonoRegState *rs, int reg)
{
if (reg >= 0) {
- rs->ffree_mask |= 1 << reg;
+ rs->ffree_mask |= (regmask_t)1 << reg;
rs->fsymbolic [reg] = 0;
}
}
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