DASIP Conference 2008 News > Industrial Sessions

[training]

Title: ECSI Workshop on TLM Users Experience

Conference on Design and Architectures for Signal and Image Processing DASIP 2008   http://www.ecsi.org/dasip   Maison Université Libre de Bruxelles, Belgium November 24-26, 2008   Advance registration deadline: November 19, 2008     DASIP Industrial Sessions   Session 1: Advances in Reconfigurable Technology This session focuses on how the industry grasps the algorithm-architecture matching challenge and will present practical solutions applied to system design, case studies and real-size industry projects based on the new reconfigurable technology development. Insights to the advances in reconfigurable devices will be provided by major technology providers. In this session two presentations will be given:     Low Power Systems on Programmable Chips Patrizio Piasentin (Actel) www.actel.com   Low power design techniques are critical for many product differentiator. Imagine portable devices were you will have 10x more time before charging. Imagine power supplied equipment were you will not need anymore a fan to cool them down. Bottom line often the question will come down to which algorithm, technology, architecture, hardware/software trade offs will optimize power efficiency. This talk will give you ideas on how System on Programmable Chip (SoPC) will help you achieve low power systems.   Xilinx Technology for Signal and Image Processing Eddy De Waegeneer (Xilinx) www.xilinx.com     Monday - November 24, 2008 - 11:30-12:30     Session 2: ESL Methods and Tools for Signal and Image Processing This session is devoted to the presentation of the novel design methods, evolving specification and modeling methods, as well as the most advanced EDA tools offered on the market for image and signal processing application development. Focus will be given on the applied design techniques and features. Demonstration of tools and direct discussion with providers will be made possible within the frame of DASIP.   Architectural Exploration of 2D-IDCT using FPGA and High-level Synthesis Pierluigi lo Muzio. DSP Specialist Application Consultant, Synopsys Europe www.synopsys.com   This paper investigates the implementation of 8x8 2D-IDCT on any FPGA technology using a different approach. The algorithm is described at high level using Simulink environment and Synplify DSP generates automatically different RTL implementations for different frame formats and different FPGA technologies. The advantage of this method consists of the possibility to explore automatically different hardware architectures using a common golden source, which is the algorithm description in Simulink. The architectures are automatically optimized for different technologies and for different speed requirements.   Architecture Exploration with CoFluent Studio Vincent Perrier, CoFluent Design (presenter TBC) www.cofluentdesign.com     Wednesday - November 26, 2008 - 10:00-11:00     Conference Program Update!   The conference features 32 high-quality papers and 14 posters that highlight the latest work occurring in the area of design and architectures dedicated to signal and image processing. More details concerning the DASIP'08 technical program and the registration can be found on the conference website, http://www.ecsi.org/dasip/.     Advance Registration   Please note that the deadline for advance registration is November 19, 2008. Take the advantage of lower registration fee!   On-line registration: www.ecsi.org/dasip     Please, transfer this message to persons interested in this topic!   We apologise if you've received multiple copies of this message!   If you don't wish to receive e-mails concerning the ECSI activities, please reply to this message with the subject REMOVE.

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