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FDL'06
Forum on specification & Design Languages
September 19-22, 2006 - TU Darmstadt, Germany
with
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High-Level Synthesis (HLS) Workshop
on September 18th, 2006 - Room C110
www.ecsi-association.org/ecsi/events/hls/ECSI-HLS.pdf
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14th European SystemC Users Group Meeting
on September 19th, 2006 - 15:00-18:00 - Room C120
www-ti.informatik.uni-tuebingen.de/~systemc
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Registration and additional information at: www. ecsi.org/fdl
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FDL06
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General Chair:
Prof. Sorin A. Huss, TU Darmstadt, Germany, [EMAIL PROTECTED]
An ECSI event - co-sponsored by TU Darmstadt
co-sponsored with no financial implication by Accellera, Cadence, GI,
GMM, IEE, IFIP 10.5, ITG, Mentor Graphics, Microswiss Network, Synopsys
FDL is the premier European forum to present research results,
to exchange experiences, and to learn about new trends in the application
of specification and design languages as well as of associated design
and modelling methods and tools for integrated circuits, embedded
systems, and heterogeneous systems.
Modelling and specification concepts push the development of new
methodologies for design and verification to system level, they thus
provide the means for a model-driven design of complex information
processing systems in a variety of application domains.
The aim of FDL is to cover several related thematic areas and to give an
opportunity to gain up-to-date knowledge in this fast evolving area.
FPD TA: Formalisms for Property-Driven Design: Verification of functional
behaviour, generation of test stimuli, model checking on the reachable
state space, and direct synthesis from assertions are main topics of
interest in this TA.
CSD TA: C/C++ Based System Design: Design methodologies that use C/C++
or dedicated modelling languages such as SystemC, SystemVerilog, Verilog,
and VHDL jointly with verification languages such as e or PSL/Sugar for
the design and verification of hardware/software systems.
AMS TA: Analog, Mixed-Signal, and Heterogeneous System Design: Design
methodologies that exploit a mix of continuous-time and discrete-event
modelling languages such as VHDL-AMS, Verilog-AMS, SystemsC-AMS,
or Modelica for the design and verification of heterogeneous systems.
UML TA: UML-Based System Specification and Design: Specification and design
methodologies such as the Model Driven Architecture that rely on UML to map
abstract models of complex embedded systems to programmable hardware
platforms and to System-on-a-Chip architectures.
FDL06 will also offer a number of high-quality tutorials, of special
sessions, and of keynotes presented by experts in their fields. Fringe
and private meetings will also be accommodated. We will try our best to
provide a nice working environment, a friendly atmosphere, and an exciting
social event to all attendees of FDL06.
FDL SECRETARIAT
Secretariat: ECSI Office
[EMAIL PROTECTED]
www.ecsi.org/fdl
Ph: +33 4 76 63 49 34
Fx: +33 4 76 42 87 87
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HLS Workshop
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ECSI Institute & UBS Workshop on
High-Level Synthesis
September 18, 2006 - 9:00-19:00
TU Darmstadt, Germany
Registration deadline: September 12!
Objectives
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The successful usage of Hardware Description Languages like VHDL and
Verilog in the design flow is mainly due to the availability of efficient
synthesis methods and tools that enable the translation of RTL designs into
optimized gate-level implementations. Many expect that the same approach
could be effectively adapted at higher levels of abstraction despite the
failure of previous attempts to behavioural synthesis from higher-level
descriptions.
Languages like C or SystemC offer high abstraction level. However, in order
to provide the designers with an efficient automated path to
implementation, new high-level synthesis tools are required. Several
commercial and academic C/C++/SystemCbased tools are available today: the
Agility Compiler and DK Design Suite from Celoxica, eXCite from Y
Explorations, CatapulC from Mentor Graphics, Cyber from Nec, PICO from
Synfora, Cynthesizer from Forte Design Systems, Cascade from Critical Blue&
SPARK from the UCSD, GAUT from the UBS&
The main expectations from the system design teams concern both methods and
tools supporting better management of the design complexity and reduction
of the design cycle all together, breaking the trend to compromise
evaluation of various design implementation options. Designing at higher
levels of abstraction is an obvious way as it allows to better managing the
system design complexity, to verify earlier in the design process and to
increase code reuse.
Thus, users formulate several crucial questions with regard to system
synthesis:
Is the so-called high-level synthesis an appropriate and efficient solution
to get to the implementation?
Is it optimal (how efficient is the RTL architecture, targeted to
downstream synthesis tools)?
What benefit can users gain and at what price: how does it influence the
designer productivity, the design flow and the way of exploring multiple
implementation alternatives, trade-off management&?
What about the verification flow (reuse of test-bench, back-annotation from
implementation to specification)?
How can IP reuse be strengthened by high-level synthesis: automatic
retargeting to different technologies, exploration of implementation
alternatives and trade-offs?
The ECSI & UBS Workshop on High-Level Synthesis HLS will provide an
overview of existing and emerging solutions provided by both industrial
partners (EDA companies) and research institutions in this domain. It will
give an outline (as complete as possible) of HLS methods and tools
available currently on the market bring the details on their applicability,
performance and strengths. Finally, the event will create a discussion
platform for experience exchange between participants.
Programme
-------------
Session 1: HLS INTRODUCTION
The Challenge of Hardware Synthesis from C-like Languages - Stephen
Edwards, Columbia University, USA
Synthesis from High level HDLs: Lessons Learnt- Rajesh Gupta, University
of California San Diego, USA
Session 2: USER NEEDS & REQUIREMENTS
Industrial presentations from: STMicroelectronics, MBDA, Mentor, ...
Session 3: RESEARCH DIRECTIONS
Multi-Process Optimizations in High-Level Synthesis - Oliver Bringmann,
FZI, Germany
Cyber Synthesis Technology - Kazutoshi Wakabayashi, NEC, Japan
SPARK- R. Gupta, University of California, San Diego, UCSD
GAUT - Philippe Coussy, LESTER - UBS, France
Session 4: EDA PRESENTATIONS
Mentor Graphics - Mansour Amirfathi
CoWare - Achim Nohl
Forte Design - Mike Meredith
NEC - Kazutoshi Wakabayashi
Synfora - Vinod Kathail
Synplicity - Doug Amos
Session 5: Parallel Tool Demos + Networking Discussion
Workshop Information & Registration
--------------------------------------------
Workshop description, registration form, hotel and venue can be found at:
http://www.ecsi-association.org/ecsi/events/hls/ECSI-HLS.pdf
The workshop is free for ECSI Industrial & Associate Members (see
conditions on the registration form)!
Please fill-in the form found on the web page and fax it back to ECSI to
+33 4 76 42 87 87
Registration deadline: September 12, 2006
Attention: limited number of seats.
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European SystemC Users Group Meeting
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Tuesday, September 19th, 2006 15:00 - 18:00
FDL Conference 2006, TU Darmstadt, Room C120
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Dear SystemC User,
Please notice the final agenda for our 14th European SystemC
Users Group Meeting. In our extended OSCI section we will give
insights into the ongoing development and work within OSCI and
the OSCI working groups. Besides this we are looking at the future
of TLM modeling and at the transition to the SystemC IEEE 1666
standard. We of course have a SystemC User«s Forum that covers
SystemC simulation and modeling topics.
We are pleased to invite you to this event!
Additional information can also be found at:
http://www-ti.informatik.uni-tuebingen.de/~systemc
AGENDA
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15:00h Coffee Reception
15:30h Opening
Axel Braun, University of Tuebingen, ESCUG
OSCI Forum
* OSCI General Update
Mike Meredith, OSCI President, USA
* OSCI TLM Working Group Plans
Mike Meredith, OSCI President, USA
* Making the Transition to IEEE 1666 SystemC
John Aynsley, Doulos, U.K.
16:30h SystemC User's Forum
* SystemC-SystemVerilog Interaction
n.n.
* A parallel version of the OSCI SystemC kernel
Philippe Combes, University of Geneva, CH
Julien Zory, STMicroelectronics, CH
* Simulating Sensor Networks with SystemC
Alban Rrustemi, University of Cambridge, U.K.
* GreenBus
Wolfgang Klingauf, GreenSocs, DE
* Using Programmer's View Timing Annotation for the
Creation of Reusable Transaction Level Models
Tim Kogel, CoWare, BE
18:00h Closing
Axel Braun, University of Tbingen, ESCUG
18:05h Buffet & Refreshments
REGISTRATION
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If you like to participate at the 14th European SystemC Users Group
Meeting, please register by replying to this email adding your name,
address, affiliation, email address, and phone number. Note that the
number of seats is limited and registrations will be handled on a
first-come-first-serve basis. Participation will be free of charges!
Please forward this email to colleagues who are also interested in SystemC.
We are looking forward to meeting you in Darmstadt!
With best regards,
Axel Braun, Wolfgang Rosenstiel
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The 14th European SystemC Users Group Meeting is supported by
Cadence, CoWare, Celoxica, Synopsys, Mentor Graphics,
ESLX, Doulos, and the Open SystemC Initiative.
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FDL CONTACT
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More information about FDL 2006 are available at: www.ecsi.org/fdl
European Electronic Chips & Systems design Initiative (ECSI)
Parc Equation - 2, Avenue de Vignate - 38610 Gieres, France
Phone: +33 4 76 63 49 34
Fax: +33 4 76 42 87 87
E-mail: [EMAIL PROTECTED]
www.ecsi.org
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