--- ECSI Workshop on Sept 18, 2006 > High Level Synthesis ---

[training]

Title: ECSI Workshop on TLM Users Experience

Attention! Last 5 days to register Registration deadline: September 12! ECSI Institute & UBS Workshop on High-Level Synthesis September 18, 2006 - 9:00-18:00 TU Darmstadt, Germany (close to Frankfurt) in conjunction with FDL'06 Conference (www.ecsi.org/fdl) Objectives The successful usage of Hardware Description Languages like VHDL and Verilog in the design flow is mainly due to the availability of efficient synthesis methods and tools that enable the translation of RTL designs into optimized gate-level implementations. Many expect that the same approach could be effectively adapted at higher levels of abstraction despite the failure of previous attempts to behavioural synthesis from higher-level descriptions. Languages like C or SystemC offer high abstraction level. However, in order to provide the designers with an efficient automated path to implementation, new high-level synthesis tools are required. Several commercial and academic C/C++/SystemCbased tools are available today: the Agility Compiler and DK Design Suite from Celoxica, eXCite from Y Explorations, CatapulC from Mentor Graphics, Cyber from Nec, PICO from Synfora, Cynthesizer from Forte Design Systems, Cascade from Critical Blue& SPARK from the UCSD, GAUT from the UBS& The main expectations from the system design teams concern both methods and tools supporting better management of the design complexity and reduction of the design cycle all together, breaking the trend to compromise evaluation of various design implementation options. Designing at higher levels of abstraction is an obvious way as it allows to better managing the system design complexity, to verify earlier in the design process and to increase code reuse. Thus, users formulate several crucial questions with regard to system synthesis: Is the so-called high-level synthesis an appropriate and efficient solution to get to the implementation? Is it optimal (how efficient is the RTL architecture, targeted to downstream synthesis tools)? What benefit can users gain and at what price: how does it influence the designer productivity, the design flow and the way of exploring multiple implementation alternatives, trade-off management&? What about the verification flow (reuse of test-bench, back-annotation from implementation to specification)? How can IP reuse be strengthened by high-level synthesis: automatic retargeting to different technologies, exploration of implementation alternatives and trade-offs? The ECSI & UBS Workshop on High-Level Synthesis HLS will provide an overview of existing and emerging solutions provided by both industrial partners (EDA companies) and research institutions in this domain. It will give an outline (as complete as possible) of HLS methods and tools available currently on the market bring the details on their applicability, performance and strengths. Finally, the event will create a discussion platform for experience exchange between participants. Programme  Session 1:  HLS INTRODUCTION The Challenge of Hardware Synthesis from C-like Languages - Stephen Edwards, Columbia University, USA Synthesis from High level HDLs: Lessons Learnt- Rajesh Gupta, University of California San Diego, USA    Session 2:  USER NEEDS & REQUIREMENTS Industrial presentations from: STMicroelectronics Mentor MBDAF   Panel discussion (30min)  Session 3:  RESEARCH DIRECTIONS   Multi-Process Optimizations in High-Level Synthesis - Oliver Bringmann, FZI, Germany Cyber Synthesis Technology - Kazutoshi Wakabayashi, NEC, Japan SPARK- R. Gupta, University of California, San Diego, UCSD GAUT - Philippe Coussy, LESTER - UBS, France    Session 4:  EDA PRESENTATIONS   Mentor Graphics - Mansour Amirfathi CoWare - Achim Nohl Forte Design - Mike Meredith NEC - Kazutoshi Wakabayashi Synplicity - Doug Amos Synfora - Vinod Kathail  Session 5:  Parallel Tool Demos + Networking Discussion   Parallel Tool Demonstrations Discussions Networking and contacts with presenters & participants   Workshop Information & Registration Workshop description, registration form, hotel and venue can be found at: http://www.ecsi-association.org/ecsi/events/hls/ECSI-HLS.pdf   The workshop is free for ECSI Industrial & Associate Members (see conditions on the registration form)! Please fill-in the form found on the web page and fax it back to ECSI to +33 4 76 42 87 87 Registration deadline: September 12, 2006 More information          For any additional inquiries, please contact:                 ECSI Office                 Parc Equation   -   2, Avenue de Vignate   -   38610 GIERES, France                 Ph: +33 476 63 49 34   -   Fax: +33 476 42 87 87   -   Email: [EMAIL PROTECTED]    -   http://www.ecsi.org Proceedings         All workshop  participants will obtain the electronic version (PDF files)  of all presentations after the workshop is finished.         The presentations will be downloadable from the ECSI web page.  Note         We respect your privacy.          If you would like to be removed from the e-mail list, please send a message to [EMAIL PROTECTED] with the subject "REMOVE". Questionnaire: If you are interested and cannot come, please give us a hint: the date is not convenient:    yes/no the place is not convenient:   yes/no       What other subjects in system design would you be interested in: ___________       Thank you!

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